I have been doing some tests to assess the AD2 analog-in performance. To this end I hooked up a signal generator to the AD2 and captured raw signals (using the FDwfAnalogInSample16 API function).
If I set my signal generator to be at DC, just be a bit above the range of the analog-in channel, and sample at 100 kHz using the Decimate filtering mode I consistently get back the value "32764" as a sample value.This conforms to my expectation: it's just the maximum value that the 14-bits ADC can output (16383), multiplied by 4 to go from 14 to 16 bits range (65532), then subtracting 32768 to make the range symmetric around 0, yielding, indeed, the value 32764.
However, when I set the filtering mode to Average, I consistently get back the value 32760. Which is not the average of a bunch of samples that are each individually equal to 32764.
I also found that the sample averaging process does not use the lower 2 bits, unfortunately -- they are always at zero. I would have hoped that the sample averager inside the FPGA would use more than 14 bits of precision for its adder, so it could effectively use the full 16 bits that are available when transferring samples to the PC. But alas, that isn't so.
I would appreciate it if someone on the side of Digilent could look into the code that does the averaging to understand how it could ever yield the value 32760 when averaging sample values that are all 32764. It may well be that there's a bug in the sample averaging code which introduces a bias or something like that, and that would certainly not be desirable.
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Hi,
I have been doing some tests to assess the AD2 analog-in performance. To this end I hooked up a signal generator to the AD2 and captured raw signals (using the FDwfAnalogInSample16 API function).
If I set my signal generator to be at DC, just be a bit above the range of the analog-in channel, and sample at 100 kHz using the Decimate filtering mode I consistently get back the value "32764" as a sample value.This conforms to my expectation: it's just the maximum value that the 14-bits ADC can output (16383), multiplied by 4 to go from 14 to 16 bits range (65532), then subtracting 32768 to make the range symmetric around 0, yielding, indeed, the value 32764.
However, when I set the filtering mode to Average, I consistently get back the value 32760. Which is not the average of a bunch of samples that are each individually equal to 32764.
I also found that the sample averaging process does not use the lower 2 bits, unfortunately -- they are always at zero. I would have hoped that the sample averager inside the FPGA would use more than 14 bits of precision for its adder, so it could effectively use the full 16 bits that are available when transferring samples to the PC. But alas, that isn't so.
I would appreciate it if someone on the side of Digilent could look into the code that does the averaging to understand how it could ever yield the value 32760 when averaging sample values that are all 32764. It may well be that there's a bug in the sample averaging code which introduces a bias or something like that, and that would certainly not be desirable.
Cheers, Sidney
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