Arty-A7-35-Master.xdc File

[FPGAtor]

They have uploaded a constrain file with the following lines:

## Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];

Is there any description how these contrain files are built and what is the meaning of the lines shown above or of every line written in the constrain file?

Thank you.

[FPGAtor]

set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }];
WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'.
INFO: [Common 17-17] undo 'set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }];'
ERROR: [Common 17-55] 'set_property' expects at least one object.
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'.
ERROR: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK100MHZ]'.
Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced

why when I am running the above commands I am getting these errors?

[JRys]

Hello,

Let's say you've created the code file below and it requires the system clock. You could either change the clock name in your code file to match CLK100MHZ or change the name it the constraints file to match your clock name. For my example, I edited the constraints file and change the name to clk.

best regards,

John

module blinky(
    input clk,
    output led
    );
    
    reg[24:0] count = 0;    
    assign led = count[24];
    always @ (posedge clk) count <= count + 1;
    
endmodule