FPGAtor

I followed that procedure (maybe with slightly different settings) before I made the post and it did not work for me. I ll give a try to this: https://digilent.com/reference/learn/programmable-logic/tutorials/cmod-a7-programming-guide/start but I still do not understand, if there is not any part of my code that is handling the spi communication and program loading on the fpga side, how the firmware is loaded from the memory during the power-on. Thank you all, I ll give a try and let you know.

Dear All, Is it possible to load a simple program in verilog on the cmod a7-35t so that you don't have to program the device after each power on-off cycle without using Microblaze firmware set-up? The process described in here (https://digilent.com/reference/learn/programmable-logic/tutorials/htsspisf/start) assumes that user implements the microblaze, sth that I do not need. Does the memory requires an SPI module implementation in your FPGA dedicated to communicate with the external memory in order to load the project of your design and the FPGA? Thank you.

Hi all, I just managed to make the blink led project to work. If I unplug the board from the host usb port and then plug it again the board is not working and I have to reprogram the device again to work. What is the reasoning for this? Shall I add a reset input utilizing one of the on-board buttons or it is sth else that is happening? Which pin would be most appropriate for reseting the device? Thank you.

set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. INFO: [Common 17-17] undo 'set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }];' ERROR: [Common 17-55] 'set_property' expects at least one object. Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object. create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }]; WARNING: [Vivado 12-584] No ports matched 'CLK100MHZ'. ERROR: [Vivado 12-4739] create_clock:No valid object(s) found for '-objects [get_ports CLK100MHZ]'. Resolution: Check if the specified object(s) exists in the current design. If it does, ensure that the correct design hierarchy was specified for the object. If you are working with clocks, make sure create_clock was used to create the clock object before it is referenced why when I am running the above commands I am getting these errors?

They have uploaded a constrain file with the following lines: ## Clock signal set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100] create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }]; Is there any description how these contrain files are built and what is the meaning of the lines shown above or of every line written in the constrain file? Thank you.