Hardware code for zmod adc-next

[Riccardo]

Hello everyone, some of you may know me from this topic 

I'm currently doing my own design in order to perform a 100s acaquisition with a changing sampling frequency over time with an Eclypse z7 boundled with Zmod ADC1410.

In order to test my first HW code I tried with the code used in zmod adc-next (https://github.com/Digilent/Eclypse-Z7-SW/tree/zmod_adc/next), but it did not work.

I was wondering if I could open the hardware configuration of that project, but downloading from git (https://github.com/Digilent/Eclypse-Z7-HW/tree/zmod_adc/next) it is impossible to open it in vivado 2019.1.

Is here someone who managed to open it? 
 

 

EDIT:

furthermore, whenever I try to chenge something/restart the procedure to flash by usb the FPGA, I manage to program the FPGA, but then when it's time to run the code I receive this

Even if I designed the HW code on vivado 2021.1 (I'm using vitis 2021.1 for the SW code).

The first time I managed to let the code run (but not to work!) I had to restart my pc.

Edited October 25, 2022 by Riccardo

[artvvb]

Hey Riccardo, 

In order to open this project in a newer version of Vivado, you would need to first install the version it was designed in (2019.1), check it out in order to get the XPR project file generated, then open that project file in your newer version of Vivado. From there, you need to upgrade all IPs to whatever newer version Xilinx has included in the install, and hope that nothing has changed so significantly that the project breaks.

I ran through this process a while back for 2020.2 and posted an archive with the resulting XPR. You can download that file and open it in 2021.1, then follow the same update process described above - this lets you skip installing that older version.

Thanks,

Arthur

[Riccardo]

Thank you artvvb!
I managed to open it and I have a question: I saw many versions of the ADC ZMod IP, in particular the ZmodADC1410_Control and the ZmodScopeController. I saw that both of them are standalone in applications where no PS is used.

I saw even the AXI adapter used in zmod adc-next to interface the ADC controller with the PS: that is the one IP that I hated when I was fighting against that buffer in the acquisition. Is there a way in order to override inside that IP or do I have to re-write that IP without that buffer?

 

Thank you for your time

Riccardo

Edited November 3, 2022 by Riccardo

[artvvb]

With Digilent IP, it's always possible to edit and repackage them to customize them for your own use, so you could use the AXI adapter as the starting point for your own design. See the screenshot below, which shows the right-click menu option that gives access to the IP Packager.

Do note that the functionality of the AXI adapter is pretty tightly coupled to the DMA in the projects it's used in - the IP fills circular buffers while waiting for a trigger, then ships data out over DMA, and doesn't do both simultaneously - and the DMA in these projects is also data-bandwidth-limited, as a higher-throughput interface was not necessary for the small acquisitions performed by the IP.

Thanks,

Arthur

[Riccardo]

Hello, I started to go through the customization of that block, in particular into the code for the circular buffer. I have a couple of questions:

I don't understant why you initialized the dina and doutb as std_logic_vector(0 downto 0) instead of std_logic_vector(13 downto 0)

 

Why is this process re-initializing all the control variables to '0' or "0" when it starts? I was finding a way to use both port of the Bram in order to read from port B while writing with port A. Is there any constraint you had to follow? I thoughted about creating a process in order to be sure to not read with portB from the same address where port A is writing and leaving the counter enable always active for both ports, do you see any criticity on this?

 

Why are there some signals that are saved many times with R and RR? Is it only a mode to create a clock cycle duration pulse on xsOutAddrCntPulse (in this case)?

Edited November 9, 2022 by Riccardo
Forgot to add a questino

[Riccardo]

On 10/27/2022 at 2:13 AM, artvvb said:

You can download that file and open it in 2021.1, then follow the same update process described above

Hello Artur, sorry if I bother you

I tried to open the project with vivado 2021.1, I migrated it following the procedure of vivado (updated all the IPs) with no modifications on the block diagram or constraints. When it comes time to open a vitis project, when I initially build the empty application (c++) project with the platform generated with the .xsa file coming from the exportation of the Hardware code I receive a makefile error: 

It seems like vitis can not generate the .elf file. Is there some warnings I have to sort out to be able to build the project?I can leave here the project in a zip file.

I tried to do this because I have the same problem on another project I'm borrowing, which uses the same IPs. In the drive folder linked there are both projects: the first one named "hv", the second one (my project) "Adc_acq_system".

https://drive.google.com/drive/folders/1OkhMl8JQ3Aqpc8SL3U86NzrDuaPovApL?usp=share_link

Thank you for your time

Riccardo

Edited November 16, 2022 by Riccardo
Forgot the link to the zip