Arty A7-100T Ethernet bitstream generation error - Vivado

[balerdi]

Hi,

I have made a simple block design in Vivado to test my Arty A7 100T's ethernet port, following Digilent's tutorial. My design includes a block design with the DDR3 block, a Microblaze, a UART and a clock wizard.

I created 3 clocks as usual with the clocking wizard: A 200MHz and a 166.667MHz for the MIG7 block and a 25MHz one for the ethernet.

Synthesis and Implementation runs fine, however, when I run bitstream generation, i get the following DRC error:

Quote

[DRC RTRES-1] Backbone resources: 1 net(s) have CLOCK_DEDICATED_ROUTE set to BACKBONE but do not use backbone resources. The problem net(s) are design_1_i/clk_wiz_0/inst/clk_out1.

Where clk_out1 is the 166.667MHz clock that comes from the clocking wizard.

Another thing that I noticed is that the ui_clk that the MIG block outputs has a frequency of 81MHz instead of 83MHz, what I think is usual.

 

Could anyone help me? Many thanks!

Edited October 25, 2022 by balerdi
more detailed title

[Anders]

I had the same problem. I started with the (more up-to-date) tutorial on https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi, which does not, however, include the ethernet parts. I followed this tutorial up to and including the step called "Add a Microblaze Processor to a Block Design". As described there, you can make a clock wizard (with input clock from the ui_addn_clk on the MIG) to generate a 25 MHz ethernet reference clock and make an external port and constrain it to the G18 pin.

From this step on, follow the tutorial you reference above (i.e., adding the board components for UART and Ethernet, and an AXI Timer, automate connections (both Ethernet/AXI timer/UART and addd Ethernet/AXI timer interrupts to Microblaze).

After this I was able to finish the bitstream generation successfully, although I also get a 81 MHz ui_clk.

I haven't yet tested it out, as I am still working on the Vitis application.

[balerdi]

I followed the tutotrial you mentioned and I was able to generate the bitstream so, many thanks Anders, I was starting to worry.

However, just to point out, the output of the clocking wizard goes to 25.003953 MHz in after just adding the Ethernet MII, UART and AXI timer blocks. And as you mentioned, ui_clk stays at 81 MHz.

Thank you again, I am also still working on the Vitis app but if I test it I will tell you too.

Edited October 26, 2022 by balerdi