balerdi

I followed the tutotrial you mentioned and I was able to generate the bitstream so, many thanks Anders, I was starting to worry. However, just to point out, the output of the clocking wizard goes to 25.003953 MHz in after just adding the Ethernet MII, UART and AXI timer blocks. And as you mentioned, ui_clk stays at 81 MHz. Thank you again, I am also still working on the Vitis app but if I test it I will tell you too.

Hi, I have made a simple block design in Vivado to test my Arty A7 100T's ethernet port, following Digilent's tutorial. My design includes a block design with the DDR3 block, a Microblaze, a UART and a clock wizard. I created 3 clocks as usual with the clocking wizard: A 200MHz and a 166.667MHz for the MIG7 block and a 25MHz one for the ethernet. Synthesis and Implementation runs fine, however, when I run bitstream generation, i get the following DRC error: Where clk_out1 is the 166.667MHz clock that comes from the clocking wizard. Another thing that I noticed is that the ui_clk that the MIG block outputs has a frequency of 81MHz instead of 83MHz, what I think is usual. Could anyone help me? Many thanks!