Jump to content
  • 0

External Reference clock


bryan78

Question

3 answers to this question

Recommended Posts

  • 0

Hi @bryan78

I don't think it matters.
In the device FPGA 2 PLLs are used to generate the requested reference (output) frequency and 2 MMCMs to obtain the system frequency from the reference (input). Two of both for higher flexibility. All these try to use the highest VCO frequency to reduce the jitter.

Link to comment
Share on other sites

Create an account or sign in to comment

You need to be a member in order to leave a comment

Create an account

Sign up for a new account in our community. It's easy!

Register a new account

Sign in

Already have an account? Sign in here.

Sign In Now
×
×
  • Create New...