I successfully downloaded, implemented and run the Mandelbrot viewer of Hamster for the Nexys Video (https://github.com/hamsternz/FPGA_Mandelbrot). The only modification I had to do was to remove Genesys2-specific components instantiated in top_level and the input/output ports related to the PMods that I don't have. The modified design works perfectly well, Hamster's work is really amazing!
At the beginning of top_level, a couple of constants allow us to configure how the Mandelbrot generator is built. I wanted to play with these constant and implement 2 multipliers (per pipeline stage) as LUTs, instead of using DSP slices. The result is a design with tighter timing (but still routable, it seems that Vivado 2016.2 improved timing for this design), but less DSP slices used.
Another difference is that the design consumes more power. When running the power analysis on the original design (many DSP slices, not so many LUTs), 5W are reported. For the modified design (less DSP slices, more LUTs), 8W are reported.
I thought that this would not be a problem, as I have a fan that does a great job at cooling-down the FPGA (45 °C for the reference design, 65 °C without the fan), but the Nexys Video board "reboots" when I try to program it with the 8W design. Basically, I program the board over JTAG, I get the message that says that programming was successful, but the board de-programs itself and returns to the original Digilent design (HDMI passthrough with temps on the LCD). If I put my bitfile on an USB thumb drive, programming works as expected, but then the board fails to run the design and re-programs itself from the USB drive (creating a programming cycle).
I have seen that the voltage regulators used on the Nexys Video allow for a maximum of 8 amps on the 1V rail (FPGA core). Could this be the root of the problem? How much can the Artix 7 A200T consume if completely filled with a high-clock-rate design (like Hamster's)? Is there any way to still allow a large and complex design to run on the board?
For reference, I have uploaded my bitfile here (the forum does not allows 6MB files to be attached to threads). This is a raw binfile for use with the Digilent Adept tools.
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steckdenis
Hi,
I successfully downloaded, implemented and run the Mandelbrot viewer of Hamster for the Nexys Video (https://github.com/hamsternz/FPGA_Mandelbrot). The only modification I had to do was to remove Genesys2-specific components instantiated in top_level and the input/output ports related to the PMods that I don't have. The modified design works perfectly well, Hamster's work is really amazing!
At the beginning of top_level, a couple of constants allow us to configure how the Mandelbrot generator is built. I wanted to play with these constant and implement 2 multipliers (per pipeline stage) as LUTs, instead of using DSP slices. The result is a design with tighter timing (but still routable, it seems that Vivado 2016.2 improved timing for this design), but less DSP slices used.
Another difference is that the design consumes more power. When running the power analysis on the original design (many DSP slices, not so many LUTs), 5W are reported. For the modified design (less DSP slices, more LUTs), 8W are reported.
I thought that this would not be a problem, as I have a fan that does a great job at cooling-down the FPGA (45 °C for the reference design, 65 °C without the fan), but the Nexys Video board "reboots" when I try to program it with the 8W design. Basically, I program the board over JTAG, I get the message that says that programming was successful, but the board de-programs itself and returns to the original Digilent design (HDMI passthrough with temps on the LCD). If I put my bitfile on an USB thumb drive, programming works as expected, but then the board fails to run the design and re-programs itself from the USB drive (creating a programming cycle).
I have seen that the voltage regulators used on the Nexys Video allow for a maximum of 8 amps on the 1V rail (FPGA core). Could this be the root of the problem? How much can the Artix 7 A200T consume if completely filled with a high-clock-rate design (like Hamster's)? Is there any way to still allow a large and complex design to run on the board?
For reference, I have uploaded my bitfile here (the forum does not allows 6MB files to be attached to threads). This is a raw binfile for use with the Digilent Adept tools.
Thanks!
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