BoxLambda, a Arty/Nexys A7-based retro-style microcomputer

[epsilon]

Hi all,

All while ago, I started BoxLambda, a Blog and open-source project with the goal of creating a retro-style FPGA-based microcomputer. The microcomputer serves as a platform for software and RTL experimentation.

https://epsilon537.github.io/boxlambda/

https://github.com/epsilon537/boxlambda/tree/develop

Does the world need another retro-style computer? Probably not, but I do. I’m a software engineer and I’ve been studying FPGA development for more than a year now, specifically for this project.

BoxLambda is a system-integration project. There's very little from-scratch RTL development. The project is mostly about studying relevant GitHub projects (CPU, graphics, sound cores etc.) and bringing them into the BoxLambda SoC.

Since the project is based on Digilent's Arty and Nexys A7, I thought some of the folks on this forum might find it interesting.

Recently, I've been working on setting up OpenOCD JTAG Debug access for BoxLambda:

https://epsilon537.github.io/boxlambda/hello-debugger/

Let me know what you think.

Cheers,

Epsilon.

[epsilon]

I just published a follow-up to my Hello Debugger post about OpenOCD JTAG Debug bring-up for my Ibex RISCV-based project.

https://epsilon537.github.io/boxlambda/openocd-loose-ends/

I included some notes about accessing the Arty A7 from Vivado running on WSL. If I recall correctly, there were some questions about that on this forum.

Cheers,

Epsilon.

 

[epsilon]

Hi all,

I integrated the LiteX SDRAM Memory Controller into BoxLambda. Here's the write-up: https://epsilon537.github.io/boxlambda/exit-mig-enter-litedram/

Cheers,

Epsilon.

[epsilon]

I integrated the VERA (Versatile Embedded Retro Adapter) core into BoxLambda: https://epsilon537.github.io/boxlambda/integrating-vera/

[epsilon]

I added an SD-Card Controller and File System to BoxLambda:

https://epsilon537.github.io/boxlambda/sd-and-fs-bring-up/

 

[epsilon]

BoxLambda Devlog: An attempt at a PicoRV32-based Soft DMA Controller

 

[epsilon]

Two Devlog updates:

An attempt at a PicoRV32-based Soft DMA Controller - Optimizations:

https://epsilon537.github.io/boxlambda/picorv32-dma-controller-pt2/

The Interconnect, Harvard Architecture, and Dual Port RAM:

https://epsilon537.github.io/boxlambda/interconnect/

 

[epsilon]

More DevLog updates:

On USB HID, Keyboard LEDs, and device emulation.

SPI Flash Access, Boot, and Core.

Hardware and Timer Interrupts.

Keeping Time: RTCC and I2C.

[D@n]

Looks like you've been having fun!

Dan (ZipCPU)

[epsilon]

Great fun. And most of it with your cores! If I were to remove all ZipCPU cores from the project, that block diagram would be very empty :-) Thank you for making ZipCPU such a great resource.

Here's my latest post. Yes, with more ZipCPU cores ;-)

Dynamically Loading a CPU in BoxLambda.

/Ruben.