Clock pin C has keep related attribute (keep/mark_debug/dont_touch) which could create extra logic on its net

[kannan.sasikumar]

I am getting the above mentioned warning during synthesis of a module. The module under consideration only has one clock and all other signals have fixed values according to different states. 

It is not a critical warning but there is an issue regarding the overall implementation of the design and there are no other significant warning and no critical warnings.

So is there a way around this warning.

 

Thanks, and Regards

Kannna 

[JColvin]

Hi @kannan.sasikumar,

I don't know what you have set up in your design or what board you are using, but this Xilinx forum thread has some good insight into your error: https://support.xilinx.com/s/question/0D52E00006hpfDKSAY/synth-85396-clock-pin-c-has-keepa-warning-that-fails-the-design-operation?language=en_US.

Thanks,
JColvin

[kannan.sasikumar]

Thanks @JColvin