kannan.sasikumar

Hi John Thank you for the replies. I am uploading the .mcs file instead of the bin file is there any difference between the two in terms of the flash programming? Also my issue regarding the power on is resolved as u mentioned my design is bigger and hence was taking more time. Thanks, and Regards Kannan

I am using a Nexys A7 board and i programmed the configurable memory device which is the spansion nor flash using the vivado ide. Upon pressing the program reset the expected code is loaded after a few secs and expected functionality is obtained, however once i power off the board the code is not loaded until i press the prog reset again once the push button is pressed the functionality works fine. So does the fpga only take the code from the external flash only upon the reset condition is it not applicable for power off. FYI the JP1 jumper is in the SPI flash position during power on.

Thanks @JColvin

I am getting the above mentioned warning during synthesis of a module. The module under consideration only has one clock and all other signals have fixed values according to different states. It is not a critical warning but there is an issue regarding the overall implementation of the design and there are no other significant warning and no critical warnings. So is there a way around this warning. Thanks, and Regards Kannna

Hello I am using the Nexys A7 development board for a project and in the schematic it is shown as having 2 SPI flash ICs present in it. I am planning to design a board using the XC7A50T-1CSG324C FPGA and is using the dev board schematic as a reference so i was wondering is the 2 SPI flashes required/necessary or is it added to improve the storage space in the Dev board. Thanks Kannan

@zygotthank u and sorry if my questions were a bit too much...

@zygot i monitored the pulse from the APD it has 4V plus and the around 1V negtv amplitudes so is there any pin in the board to which i can give this directly oru should i use a level shifter ??

@ocanturan26 which demo r u referring to??

Hi @zygot Thank you for ur suggestions i ll try with the pmod and see what happens and then move to other options as and if necessary the FPGA was the clients requirement since their previous board uses them and there are few other functionalities being implemented which have time constraints Thanks and Regards Kannan

So should i try by using the pmod pins and if it doesnt i ll try the logic required between APD and pmod?? Also could u please elaborate a bit on the 3.3V CMOS/TTL??? Thanks and Regards Kannan

Could u pls elaborate on what kind of logic design i should be implementing, should i design an impedance network for impedance matching?? Also can i use the pmod pins in the dev board to directly feed the apd out to the fpga, will the attenuation be so high that pulse will be heavily clobbered and hence undetectable?

Hi @zygot APD is an Avalanche Photo Diode, we are implementing a particle size analyzer and for that the liquid is illuminated by a laser and then when ever light hits a particle it is reflected and then APD captures it and sends out a pulse of 8ns high and then 20ns deadtime. Pulse will repeat in a non uniform fashion since pulses are generated only when a particle hits the light from the source. So i need to know if the pulse can be send to the FPGA so that a counter can count the pulses. I did not understand what u meant by logic family is it in relation to the FPGA or the APD? Thanks and Regards Kannan

For my project I have high speed pulses coming from an APD that is to processed by the FPGA, but the Nexys A7 board does not have any obvious pins to accept the fast pulses, since there are no pins with the impedance matching. So is there a way around this issue, are there any pins I can use with my pulses getting attenuated completely or will i have to use an external board just for the impedance matching before i send the pulses into the Dev board?? Thanks and Regards Kannan

@JColvin For my project I have high speed pulses coming from an APD that is to processed by the FPGA, but the Nexys A7 board does not have any obvious pins to accept the fast pulses, since there are no pins with the impedance matching. So is there a way around this issue, are there any pins I can use with my pulses getting attenuated completely or will i have to use an external board just for the impedance matching before i send the pulses into the Dev board?? Thanks and Regards Kannan

Hi @JColvin In the UART module code you have shared: -- Set Generic g_CLKS_PER_BIT as follows: -- g_CLKS_PER_BIT = (Frequency of i_Clk)/(Frequency of UART) -- Example: 10 MHz Clock, 115200 baud UART -- (10000000)/(115200) = 87 -- library ieee; use ieee.std_logic_1164.ALL; use ieee.numeric_std.all; entity UART_RX is generic ( g_CLKS_PER_BIT : integer := 115 -- Needs to be set correctly ); port ( i_Clk : in std_logic; i_RX_Serial : in std_logic; o_RX_DV : out std_logic; o_RX_Byte : out std_logic_vector(7 downto 0) ); end UART_RX; In the Generic g_CLKS_PER_BIT the calculated value is 87 however it is initialized to 115, so wont that point to a different baud rate if 115 is used rather that 87 for 115200?? Kannan