I can create a working bare metal project for a Genesys-ZU in Vitis 2022.1, but it has one issue...

[John J]

I created a script which produces a generic clean Hello World project in Vitis 2020.1 for a Genesys-ZU 3EG/5EV.  It automatically adds the custom Genesys-ZU FSBL and imports an XSA file.

The script did not appear to work in Vitis 2022.1, but it actually does.  The problem appears to be in the Digilent custom DDR initialization when used with the current tool chain, but I can easily consistently make it work.  But it's not a valid "production" solution to the issue.

When I define FSBL_DEBUG_INFO for the FSBL project in C++ Build->Settings->Symbols, DDR initialization completes properly.  I have not seen it fail in over 30 runs.  Without FSBL_DEBUG_INFO defined, DDR initialization fails every time.

This appears to be a timing issue with the custom Digilent DDR initialization.

Since I believe that I've pinned it down to a small chunk of Digilent code, that is not compatible with the current compiler, can someone take a look at this issue?  It would be really helpful.

I can provide the generic project creation script, if it will help.  It requires very little setup to use.  You just have to put the custom FSBL source files and a Vivado XSA in to specific directories and run it.

Thank you for your help.

[John J]

I was hoping that this question about being able to use Vitis 2022.1 with the Genesys-ZU would generate some interest on the baremetal user side as well as the with the Digilent staff members, but all is quiet.

Ping.

[BogdanVanca]

Hi @John J,

I'm sorry for my late response.

The generic project creation script will be very helpful.  To make everything a little bit more clear, the system initialization trough psu_init() is returning  back an DDR initialization error, and when you are enabling the debug prints by adding the FSBL_DEBUG_INFO symbol, this error is disappearing? 

If this is the case, I have to somehow recreate your setup, because I'm not experiencing the same issue on my local machine. You also said that you are experiencing this in 2022.1, and you didn't had problems in 2020.1, am I right?

Best regards,

Bogdan Vanca

[John J]

Hi @BogdanVanca.

To answer your question about psu_init(), I believe you are correct, but it has been a couple of weeks since I was trying to debug it.  I know that I tracked it down to the about the lowest level if statement where the failure happens, but I did not make note of it as I did not have the time to do the research to properly debug it.

I'm providing the script in the attached zip file, as well as the directory structure, a copy of the Digilent FSBL, and my hardware files needed to use with the script.   The hardware files include a Vivado built Genesys-ZU 3EG XSA file with it's Vivado 2022.1 project, but you can use your own, if you properly name it by replacing the one that is included.

Note:  I wrote the script for Linux, I have not thought about what needs to be done to run it in Windows.

Note:  In Vitis, you will have to rebuild the FSBL, re-select the FSLB ELF in the platform project, rebuild the platform, rebuild the boot and system projects to run or debug the code in Vitis.  I have not figured out how to get around that yet.  The script tries to do it, but it does not quite work yet.

If you unzip the file in your Linux home directory, you will end up with the following directory and file under ~/source.  The details are documented in the script.

• ~/source/MyProj_MyApp/*
• ~/source /CreateVitisProject.tcl

At that point you  can source the Vitis settings64.sh for the Vitis version that you would like to work with and run the script.

xsct ~/source/CreateVitisProject.tcl

Using the script, in Vitis 2020.1, The hello world app successfully runs.  In Vitis 2022.1 with only rebuilding the projects as generated by the script, I get the following output followed by the standard memory write error when the app tries to load.

XFSBL_DDR_INIT_FAILED
Fsbl Error Status: 0x3FFFFFFF
Fallback not supported
Exit from FSBL

If I define FSBL_DEBUG_INFO in the FSBL project properties, and make sure I rebuild the FSBL, reselect the FSBL ELF in the platform project and rebuild the platform project. I get the following output.

Note:  This IS Vitis 2022.1.  I did not update SDK_RELEASE_YEAR the Digilent FSBL code.

Xilinx Zynq MP First Stage Boot Loader
Release 2020.1   Aug 25 2022  -  17:32:52
Reset Mode      :       System Reset
Platform: Silicon (4.0), Cluster ID 0x80000000
Running on A53-0 (64-bit) Processor, Device Name: XCZU3EG
Digilent Genesys ZU board-specific init
Processor Initialization Done
================= In Stage 2 ============
In JTAG Boot Mode
================= In Stage 4 ============
PMU-FW is not running, certain applications may not be supported.
Protection configuration applied
PL Configuration done successfully
Exit from FSBL
Hello World
Successfully ran Hello World application

I have repeated this project creation process over 30 times, and run the generated apps many more times over with the same result every time--as long as I follow the procedure.

See the header in the script to find out how to use and customize it.

While the XSA files are in the ZIP file, the 3EG/5EV hardware projects can be modified/rebuilt with Create HDL wrapper, Generate Output Products, Generate Bitstream and Exporting Hardware while including the bitstream.

Let me know if you have any further questions.

I appreciate your help.

CreateProjScript.zip

Edited August 29, 2022 by John J

[John J]

@BogdanVanca

In this attachment, I've added a project for the Genesys-ZU 5EV board in addition to the 3EG.  You just have to change board_type in the script to create a project for the 5EG board.

I have been working with the 3EG board and wanted to verify that the behavior on the 5EV is the same as the 3EG.  It is.  I've tested this on two Linux systems with Ubuntu 20.04 and 22.04 and under different user accounts.

Both of the projects probably have UART1 enabled and mapped to EMIO pins.  As @JColvin is working on an issue related to UART1.

Thank you for your help.

CreateProjScript-3eg-5ev.zip

Edited August 26, 2022 by John J

[BogdanVanca]

Hi @John J,

Thank you very much for the script. We are also providing a very similar approach with our vitis-scripts

Can you please tell me what DDR4 module you are using?  I'm not been able to replicate your issue on my local machine. 

I've published  the release for the Hello-World app for our 5EV variant in 2022.1 here

Can you please move on to the 5ev/master branch and build the project with our scripts? (You can also use your script, but please make sure that you are using the right fsbl sources, check the attached zip)

Steps are :

git clone --recursive <URL>

cd Genesys-ZU/

git switch 5ev/master

git submodule init

git submodule update

cd sw/

git submodule init

git submodule update

Launch the Xilinx Vitis 2022.1 and open the XSCT Console.

source [getws]/../src/checkout.tcl

If you open this script you will see that is more or less similar to the one the you provide me, the only difference is that is building the FSBL app from scratch.   For now, I cannot pinpoint anything but I will continue my investigation and I will keep you updated.

src.zip

[John J]

Hi @BogdanVanca

The FSBL code that I have been using was from 3eg/master.  I did see that the 5ev/master code had been updated, but I didn't see much in the commit messages that stated what had actually changed.  I'll have to look at the differences, when I get a chance.  Please update the master/3eg branch.

I was not able to run the Digilent checkout.tcl script.  The domain's BSP is missing the required FSBL libraries.  I could have added them in, but I just used my script.

xsct% Specified template name Zynq MP FSBL is not valid for configuration. Reason: These libraries which FSBL requires are missing in Board Support Package: xilffs xilsecure xilpm. List of valid names are Dhrystone, Memory Tests, Peripheral Tests, Image Selector, Empty Application(C), Zynq MP DRAM tests, Hello World.

My 5EV and 3EG boards both have the HX424A14IB/4 DDR4 modules.

The 5ev/master FSBL code appears to work for both the 5EV and 3EG boards using my script without the extra debug output.

Thank you for your help.

Edited August 29, 2022 by John J