Arty A7 35t and Vivado 2022.1 Microblaze clocks

[djt294]

Hi,

I have been trying to generate a bitstream for the ArtA7-35t. I instantiaede a Microblaze processor. I am using the diligent xdc file, uncommenting the clock lines  and renaming the clk pin on the block diagram to sys_clk_pin:

## Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { CLK100MHZ }]; #IO_L12P_T1_MRCC_35 Sch=gclk[100]
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { CLK100MHZ }];
 

I am getting these errors:

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 9 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: sys_clk_pin_clk_p, and sys_clk_pin_clk_n.

 

It seems as though the microblaze uses a diff clk but the xdc clk is singled ended. I tried running with out the constraints file, just the board presets and got the same results.

Help would be appreciated.

thanks

[rjr1287]

I suggest you follow the instructions at the following site: 

https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi

If I recall correctly, I was getting the same error because I was following a different tutorial for an older version of Vivado.