rjr1287

I suggest you follow the instructions at the following site: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi If I recall correctly, I was getting the same error because I was following a different tutorial for an older version of Vivado.

I think the point was that you could use some other pins to allow you to have two UARTs, one to connect to the other board, as you want, and another one to connect to a computer, if that's needed. You would need to create a cable to go from the two pins on one board to the two pins on the other board (output to input), but you would need that even if you used the standard pins. I'm not familiar with the board you're using, but if C4 is the output pin and D4 is the input pin (on both boards), you would need to wire it up so that C4 on one board is connected to D4 on the other board. Since the UART IP uses the AXI interface, it might be easiest to have a MicroBlaze processor to move the data from one address space to another, but I would bet there is a way to do it completely within the FPGA (I'm not an expert). Or, I've found simple UART VHDL code available (search the internet) that has a much simpler interface. Data movement can be done completely within the FPGA very easily.

Using Vivado 2018.2, I followed the tutorial "How To Store Your SDK Project in SPI Flash", and it worked fine on our ARTY A7-100 board (even though it is meant for the Nexys 4 DDR FPGA Board). However, I'm trying to now use Vivado 2020.2, and the instructions no longer work. The instructions say that, after creating the Vivado project, export it and open Vivado SDK. At some point between 2018.2 and 2020.2, Xilinx replaced Vivado SDK with Vitis, so I opened Vitis. Now I'm at the point in the tutorial "SDK Steps to create a bootloader and program the board". Vitis has a different method to create projects, but I have a bootloader project using the "SREC SPI Bootloader" template. Now comes the problem. The instructions say to configure the BSP to set the "serial_flash_family" and "serial_flash_interface" within the "xilifs library". There is no "xilifs library" in the BSP. I'll also note that the tutorial has a screen shot from the "Templates" selection screen that says "Update the serial_flash_family and serial_flash_interface in xilisf library in BSP settings!". The comments no longer say that. So I assumed it was no longer necessary and continued without updating anything in the BSP settings. After building the bootloader (and an application), I followed the instructions for creating the ".bit" file with the bootloader (slightly different with this version of the toolset, but not very different), and programmed the flash with the ".bit" file and my SREC version of the application. I will note that, when I program the FPGA using the Vitis debugger, the application runs with no problems. When I reset the board with the program in flash, the application does not work (nothing goes to the serial port; no TCP connections are made). I used the debugger, which appears to automatically connect to the board, and hit the "interrupt" button. The program appeared to stop, and showed assembly language instructions with a location of 0 (which is where the bootloader starts). The instruction listed at that location is kind of strange: R0 is added to R0 and put in R0. The next instruction is an immediate jump to location 0. So, it is in a loop doing nothing. Thinking that perhaps I did not program the flash correctly, I repeated that set of steps using the 2018.2 version of the ".bit" file and SREC version of that application. A reset caused the system to work correctly. I saw text on the console and was able to connect using TCP test messages. Is there something needed that I missed?