Writing Directly to ZMOD Port Pins on Eclyspe Z7

[atown622]

I am trying to bypass using the buffer feature on the DAC I have attached to the Eclypse Z7 by writing directly to the DAC pins (which are connected to the ZMOD port).  I am having trouble finding the register manual for this such that I can write directly to the 14 bits of the ZMOD port that are connected to the DAC.

I have found the base address of the ZMOD_PORT (0x43C1000) but do not know how much of an offset value I would need to access the address in which the 32 pins are controlled.

I have been diving deep into the code file trying to find what this offset would be, but am so far coming up empty.  Does anyone possibly have the link for the register manual for the Eclypse Z7 ZMOD?

I know ive been asking a lot of questions, sorry and thanks for your time.  (This is for my senior project which I was assigned, so like I have to deal with what I got.)

[artvvb]

In published software demos, the 14-bit data bus is connected to the Zmod AWG/DAC low-level IP, which provides an AXI4-stream interface through which data is sent. There is no PS-connected register which would bypass the DMA, high level IP, or the AXI4-stream interface. The base addresses you see in software correspond to AXI peripherals that are connected to the PS, not necessarily any register in the PL. You will be limited by the capabilities of whatever is implemented in the FPGA fabric. The manual for the Zmod DAC AXI Adapter can be found on the Zmod AWG's resource center, or through the IP configuration wizard in Vivado - the latter will get you the most accurate version of the manual for the version of the IP you are working with. Double-click on the IP you want to see documentation for, and in the window that pops up and check the top left corner for a "Documentation" dropdown.

In short, sending data directly to the data bus without going through the data paths implemented in the hardware platform you have access to would require you to modify the hardware platform by modifying the Vivado project, which is not necessarily a simple process.

You could potentially get direct access to the AXI4-stream interface and develop an HDL module to generate data and send it to the port by adapting the Low-Pass Filter demo, which instantiates the low-level IPs without any connection to the PS, however this would mean you would not be writing software for the PS at all, and would be working primarily in RTL.

Thanks,

Arthur

[atown622]

18 hours ago, artvvb said:

In published software demos, the 14-bit data bus is connected to the Zmod AWG/DAC low-level IP, which provides an AXI4-stream interface through which data is sent. There is no PS-connected register which would bypass the DMA, high level IP, or the AXI4-stream interface. The base addresses you see in software correspond to AXI peripherals that are connected to the PS, not necessarily any register in the PL. You will be limited by the capabilities of whatever is implemented in the FPGA fabric. The manual for the Zmod DAC AXI Adapter can be found on the Zmod AWG's resource center, or through the IP configuration wizard in Vivado - the latter will get you the most accurate version of the manual for the version of the IP you are working with. Double-click on the IP you want to see documentation for, and in the window that pops up and check the top left corner for a "Documentation" dropdown.

In short, sending data directly to the data bus without going through the data paths implemented in the hardware platform you have access to would require you to modify the hardware platform by modifying the Vivado project, which is not necessarily a simple process.

You could potentially get direct access to the AXI4-stream interface and develop an HDL module to generate data and send it to the port by adapting the Low-Pass Filter demo, which instantiates the low-level IPs without any connection to the PS, however this would mean you would not be writing software for the PS at all, and would be working primarily in RTL.

Thanks,

Arthur

I have managed to do the editing to the Vivado file.  Just trying to figure out how to send different voltages with the enable bit pulse high or low.