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Repurposing Arty-A7 as a JTAG ISP


TomF

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Hi @TomF,

In principle I suppose this is possible to do. The on-board FTDI chip has been configured with various ID information identifying it as the original device, so if Vivado/Vitis does not throw a fit about the downstream FPGA being different than expected (I'm not certain if/how Vivado would know, it depends on how Vivado confirms that a selected bitstream matches the target FPGA device).

I don't know your particular situation, but it may be easier to just get an external JTAG programmer (like the JTAG HS2 or any other kind programmer that is compatible with the Xilinx toolset).

Thanks,
JColvin

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