Arty-S7 AXI with MIG DDR3 dual clock Example or Tutorial?

[Tim S.]

Hi,

I purchased an Arty-S7-25. I have three small HDL-only examples that I created, where I ported an Arty-A7-100 design to Arty-S7-25.

https://github.com/timothystotts/fpga-serial-acl-tester-3

Now I am looking to make a Microblaze AXI design equivalent, as I did for the other board. Can someone at Digilent point me to where I should look for creating a MicroBlaze AXI + DDR3 design for the Arty S7-20? Specifically, I am not familiar with using both the System Clock and the DDR clock for the DDR3L MIG. Are Digilent customers expected to read through the Xilinx documentation on MIG, DDR3, etc, to understand the nuances of using two external clocks for the MIG? Or has Digilent posted an example that uses the Clocking Wizard and MIG with the two separate clocks? Thanks.

Tim S.

[JColvin]

Hi @Tim S.,

Zygot is not wrong in terms of the that guide he linked being the only real link to an all HDL design using the DDR present on a Digilent website.

I'm not entirely certain what you are asking (are you asking how to use both the 12 MHz and the 100 MHz clock in a design)?

If you want to use the Microblaze block design flow to integrated DDR on an Arty S7 (that does not use both clocks), I would use the Getting Started with Vivado IPI guide, https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi. This flow takes the 100 MHz clock into the sys_clk_i input on the MIG, and loops provided (via the board files) additional 200 MHz UI clock from the MIG itself to its clk_ref_i input. Any other IPs needing a clock input of some kind (like Microblaze) are fed the provided ui_clk output (I think this is at 81 MHz for the Arty S7). Other individual clock frequencies (like some of the slower frequencies that some of the ICs on Pmods need) can be created from a clocking wizard that is downstream of the ui_clk and the associated reset from the MIG.

Thanks,
JColvin

[zygot]

As far as I know, this is the only attempt at a general purpose HDL flow DDR tutorial: https://forum.digilent.com/topic/22197-a-guide-to-using-ddr-in-the-all-hdl-design-flow/

I haven't used the Spartan 7 devices yet but the tutorial is supposed to be general and interactive.

You will have to be familiar with the external memory controller IP for your device; that is you will have to do some homework. Perhaps the link will save you some time.

My expectation is that there is different DDR IP for Spartan 7, just as the IP for UltraScale devices is different from Series 7 devices. Edited March 28, 2022 by zygot