What to do with unconnected port signals

[Hartley]

Hello all,

I have a HDL design that has a 16-bit inout port. Unfortunately the dev board (Arty Z7) I am using does not have enough I/O pins for me to constrain all the signals in the 16-bit port. I'm using all the other I/O pins already for other parts of the design.

On a similar design using a Spartan3e and the Xilinx ISE 14.7 tools, I was able to handle the unconnected signals in a port in the .ucf file like this:

NET "PA<0>"     LOC = "D9"  | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<1>"     LOC = "B10" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<2>"     LOC = "E6"  | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<3>"     LOC = "P12" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<4>"     LOC = "D12" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<5>"     LOC = "E9"  | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<6>"     LOC = "C10" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<7>"     LOC = "D1"  | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<8>"     LOC = "D10" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<9>"     LOC = "D11" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<10>"    LOC = "C12" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<11>"                  IOSTANDARD = LVTTL | PULLDOWN ;
NET "PA<12>"    LOC = "F9"  | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<13>"    LOC = "B16" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<14>"    LOC = "E11" | IOSTANDARD = LVTTL | PULLUP ;
NET "PA<15>"                  IOSTANDARD = LVTTL | PULLDOWN ; 

I tried doing the same thing in the constraints file:

set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}]
set_property PULLDOWN true [get_ports {PA[0]}]
set_property PACKAGE_PIN W14 [get_ports {PA[1]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}]
set_property PULLUP true [get_ports {PA[1]}]

set_property PACKAGE_PIN V12 [get_ports {PA[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}]
set_property PULLUP true [get_ports {PA[2]}]

set_property PACKAGE_PIN V16 [get_ports {PA[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}]
set_property PULLUP true [get_ports {PA[3]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}]
set_property PULLDOWN true [get_ports {PA[4]}]

set_property PACKAGE_PIN Y14 [get_ports {PA[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}]
set_property PULLUP true [get_ports {PA[5]}]

set_property PACKAGE_PIN W13 [get_ports {PA[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}]
set_property PULLUP true [get_ports {PA[6]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}]
set_property PULLDOWN true [get_ports {PA[7]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[8]}]
set_property PULLDOWN true [get_ports {PA[8]}]

set_property PACKAGE_PIN T11 [get_ports {PA[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PA[9]}]
set_property PULLUP true [get_ports {PA[9]}]

set_property PACKAGE_PIN T10 [get_ports {PA[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {PA[10]}]
set_property PULLUP true [get_ports {PA[10]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[11]}]
set_property PULLDOWN true [get_ports {PA[11]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[12]}]
set_property PULLDOWN true [get_ports {PORTA[12]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[13]}]
set_property PULLDOWN true [get_ports {PA[13]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[14]}]
set_property PULLDOWN true [get_ports {PA[14]}]

set_property IOSTANDARD LVCMOS33 [get_ports {PA[15]}]
set_property PULLDOWN true [get_ports {PA[15]}]

The Synthesis and Implementation complete successfully. But when I try to generate the Bitstream I get an error:

[DRC UCIO-1] Unconstrained Logical Port: 9 out of 158 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: PA[15], PA[14], PA[13], PA[12], PA[11], PA[8], PA[7], PA[4], and PA[0].

Is there anyway to fix or get around this? The HDL code that handles these signals also handles other 16-bit ports and I really don't want to make a "special" version just for this.

Thanks
 

[zygot]

Simply comment out any constraints for unused pins, by inserting the '#' character at the beginning of the line. I tend to create a new constraints file from the master constraints file that only references pins used in the design. As I recall the Digilent master constraints files come with all constraints commented out, so you could just start with copying the master constraints file for your board to a new file and commentating those that apply to your toplevel entity or module.

Not all vendor tools throw an DRC error for constraints that aren't connected to a design, but Vivado does.

[Hartley]

Removing the constraints for the unused pins gives me the same error.

[zygot]

It's sad but among the things that Xilinx sees fit to muck with, from version to version, is syntax for constraints. If you read the warning messages I bet you'll see a bunch of warnings about ignored constraints due to syntax errors. You can use the tcl console to get help with syntax ( sometimes you'll get suggestions that the tools will accept... ) or use the template tool. Vivado help is not always up to date with tool. If this fails you can try web searches.

It's easy to ignore warning messages as there can be hundreds of them, most ignorable, but then there are the ones that point to a serious issue; not all of these cause a bitgen failure but still produce broken implementations. So, be in the habit of reading what the tools have to say. You won't be happy unless the tools understand your instructions; at least the tools try and tell you when it's confused about its marching orders...

Edited March 1, 2022 by zygot

[Hartley]

I don't see any warnings, just the final error.

The problem is I have a top level 16-bit bus that I have made external. But I only have some of the signals constrained to pins.

PORTA_IO and PORTB_IO both only have some of the pins constrained. But, both ports are 16-bits internally to the myIP_0 design.

If I don't make the ports external I am able to generate the bitstream. But, of course, I can't output or read anything on the two ports.

Eventually I will be implementing this design on a larger Zynq device and all of the pins will be constrained. Right now I am limited by the Arty Z7 I/Os.

I have another problem with the inout ports. Right now the Implementation schematic shows them as output only:

But, that's a different problem. I need to figure out the constraints issue first.

[zygot]

You can simulate a design with unconnected signals but you can't implement it. If the tools can't connect toplevel signals to an IO pin there's no implementation or bitstream.

What you might be able to do is connect your IO to VIO IP and use the Hardware Manager to set and detect signals. You might connect them to a UART or some other physical interface.