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Hartley

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Everything posted by Hartley

  1. I wanted 'nano' on my rootfs (because I hate vi). I found the yocto recipe was available in components/layers/meta-openembedded/meta-oe/recipes-support/nano. But I have not been able to figure out how to get that layers recipes to show up in 'petalinux-config -c rootfs'. I finally found I can get 'nano' installed by adding this to my project-spec/meta-user/conf/user-rootfsconfig: CONFIG_nano That works but is kind of annoying since it is under the 'user packages --->' instead of 'Filesystem Packages --->' in the 'petalinux-config -c rootfs'. I know need the 'libmodbus' library (components/yocto/layers/meta-openembedded/meta-oe/recipes-extended/libmodbus). It there a way to get all the components/yocto/layers/meta-openembedded/meta-oe/recipies* to show up in the configuration?
  2. My project is a baseline Baremetal project. I'm using read() to get input from STDIN to allow user input of simple commands to test my hardware design. Basically: static void read_input(char* str) { printf("> "); fflush(stdout); int index = 0; char key; do { read(1, (char*)&key, 1); switch (key) { case 0x0D: // enter printf("\r\n"); break; case 0x7F: // backspace if (index > 0) { index--; str[index] = 0x00; printf("\r \r"); fflush(stdout); xil_printf("> %s", str); fflush(stdout); } break; default: str[index++] = key; printf("%c", key); fflush(stdout); } } while (key != 0x0D); str[index] = 0x00; } The function works fine I just wanted to get rid of the annoying warning during the build. read() is normally defined in <unistd.h> but including that breaks the build due to the conflicting types for 'sleep' and 'usleep'. But, read() must be available somehow since the code does run. I was just wondering where so I can include the proper header.
  3. Hello all, I have a build warning in my code: implicit declaration of 'read'; did you mean 'fread'? [-Wimplicit-function-declaration] The code works but the warning is annoying. I tried including <unistd.h> to pull in the declaration but that results in a build failure: conflicting types for 'sleep' conflicting types for 'usleep' Does anyone know what header can be included in Vitis to correctly get the prototype of 'read'? Thanks
  4. Hello, I was using my Arty Z7 board to test some Petalinux stuff booting from a SD Card. Everything was working fine. I wanted to try some other FPGA stuff so I created a new Vivado project and switched my board to boot from JTAG. Now I am getting errors when Vivado attempts to open the taget: INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/003017A6B7F7A ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/003017A6B7F7A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors. I tried switching it back to boot from the SD card and that does not work now either. My host system is linux Ubuntu if that matters. Any ideas? Thanks Just an update on the board. I have tried powering it from both the USB and REG inputs. Both appear to work (LD13 turns on for both). I have also connected to the USB UART using 'tio -b 115200 /dev/ttyUSB1'. When tio is running I see Connected/Disconnected messages when the board is powered on/off. Also, pressing keys in tio when connected causes the TX LED to flash. So I'm guess that the USB UART is working. But, I still can't get the board to boot using the SD card that was working before. And I can't get Vivado to make a JTAG connection. Help!
  5. Hello, I am working on an app for a Zynq board (Arty Z7) using petalinux. I created the app by doing: # create the app and recipe $ petalinux-create -t apps --name <app-name> --template c # enable the app in the final image $ petalinux-config -c rootfs # edit the source in the <project dir>/project-spec/meta-user/recipes-apps/<app-name>/files # build the app $ petalinux-build -c <app-name> # build petalinux and repackage image This works but the rebuild/package of the image is a pain. Where can I find the built <app-name> executable so I can just ftp copy it to the Arty Z7? Thanks
  6. I had this issue also (and hate vi)... I found the recipie for nano in <PentaLinux project directory>/components/yocto/layers/meta-openembedded/meta-oe/recipies-support/nano. I was able to add nano to my rootfs by doing the following. Edit your <PentaLinux project directory>/project-spec/meta-user/conf/user-rootfsconfig and add: CONFIG_nano Then do: $ petalinux-config -c rootfs And enable nano under user packages. Then rebuild and package petalinux for your board. There may be another way but that worked for me. Hartley
  7. I don't see any warnings, just the final error. The problem is I have a top level 16-bit bus that I have made external. But I only have some of the signals constrained to pins. PORTA_IO and PORTB_IO both only have some of the pins constrained. But, both ports are 16-bits internally to the myIP_0 design. If I don't make the ports external I am able to generate the bitstream. But, of course, I can't output or read anything on the two ports. Eventually I will be implementing this design on a larger Zynq device and all of the pins will be constrained. Right now I am limited by the Arty Z7 I/Os. I have another problem with the inout ports. Right now the Implementation schematic shows them as output only: But, that's a different problem. I need to figure out the constraints issue first.
  8. Removing the constraints for the unused pins gives me the same error.
  9. Hello all, I have a HDL design that has a 16-bit inout port. Unfortunately the dev board (Arty Z7) I am using does not have enough I/O pins for me to constrain all the signals in the 16-bit port. I'm using all the other I/O pins already for other parts of the design. On a similar design using a Spartan3e and the Xilinx ISE 14.7 tools, I was able to handle the unconnected signals in a port in the .ucf file like this: NET "PA<0>" LOC = "D9" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<1>" LOC = "B10" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<2>" LOC = "E6" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<3>" LOC = "P12" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<4>" LOC = "D12" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<5>" LOC = "E9" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<6>" LOC = "C10" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<7>" LOC = "D1" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<8>" LOC = "D10" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<9>" LOC = "D11" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<10>" LOC = "C12" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<11>" IOSTANDARD = LVTTL | PULLDOWN ; NET "PA<12>" LOC = "F9" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<13>" LOC = "B16" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<14>" LOC = "E11" | IOSTANDARD = LVTTL | PULLUP ; NET "PA<15>" IOSTANDARD = LVTTL | PULLDOWN ; I tried doing the same thing in the constraints file: set_property IOSTANDARD LVCMOS33 [get_ports {PA[0]}] set_property PULLDOWN true [get_ports {PA[0]}] set_property PACKAGE_PIN W14 [get_ports {PA[1]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[1]}] set_property PULLUP true [get_ports {PA[1]}] set_property PACKAGE_PIN V12 [get_ports {PA[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[2]}] set_property PULLUP true [get_ports {PA[2]}] set_property PACKAGE_PIN V16 [get_ports {PA[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[3]}] set_property PULLUP true [get_ports {PA[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[4]}] set_property PULLDOWN true [get_ports {PA[4]}] set_property PACKAGE_PIN Y14 [get_ports {PA[5]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[5]}] set_property PULLUP true [get_ports {PA[5]}] set_property PACKAGE_PIN W13 [get_ports {PA[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[6]}] set_property PULLUP true [get_ports {PA[6]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[7]}] set_property PULLDOWN true [get_ports {PA[7]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[8]}] set_property PULLDOWN true [get_ports {PA[8]}] set_property PACKAGE_PIN T11 [get_ports {PA[9]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[9]}] set_property PULLUP true [get_ports {PA[9]}] set_property PACKAGE_PIN T10 [get_ports {PA[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[10]}] set_property PULLUP true [get_ports {PA[10]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[11]}] set_property PULLDOWN true [get_ports {PA[11]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[12]}] set_property PULLDOWN true [get_ports {PORTA[12]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[13]}] set_property PULLDOWN true [get_ports {PA[13]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[14]}] set_property PULLDOWN true [get_ports {PA[14]}] set_property IOSTANDARD LVCMOS33 [get_ports {PA[15]}] set_property PULLDOWN true [get_ports {PA[15]}] The Synthesis and Implementation complete successfully. But when I try to generate the Bitstream I get an error: [DRC UCIO-1] Unconstrained Logical Port: 9 out of 158 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: PA[15], PA[14], PA[13], PA[12], PA[11], PA[8], PA[7], PA[4], and PA[0]. Is there anyway to fix or get around this? The HDL code that handles these signals also handles other 16-bit ports and I really don't want to make a "special" version just for this. Thanks
  10. Hello all, Does anyone know of an example or tutorial on how to update a design from a processor bus interface to a zynq axi-lite interface? I have a design that uses a simple bus interface to a PowerPC processor. The bus interface itself is pretty simple. It uses these ports: -- Local bus clock and interrupt LCLK : in std_logic; INT : out std_logic; -- PPC5200 local bus HOST_DATA : inout std_logic_vector(15 downto 0); HOST_ADDR : in std_logic_vector(9 downto 0); HOST_CS : in std_logic; HOST_RW : in std_logic; The host interface is then handled in a single process that decodes the address bus and generates read/write strobes to four FIFOs (two read-only and two write-only, each read/write pair share an address) and two register (one read only and the other read/write). The rest of the design is a DSP with a bunch of peripherals. The host sends and reads data through the FIFOs and gets status and interrupt information using the registers. I _think_ the DSP side of the design will work as-is but I can't figure out how to convert the host interface to an axi-lite interface. Any help/suggestions would be appreciated.
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