convert a design from a processor bus interface to a zynq axi-lite interface

[Hartley]

Hello all,

Does anyone know of an example or tutorial on how to update a design from a processor bus interface to a zynq axi-lite interface?

I have a design that uses a simple bus interface to a PowerPC processor. The bus interface itself is pretty simple. It uses these ports:

        -- Local bus clock and interrupt
        LCLK            : in    std_logic;
        INT             : out   std_logic;

        -- PPC5200 local bus
        HOST_DATA       : inout std_logic_vector(15 downto 0);
        HOST_ADDR       : in    std_logic_vector(9 downto 0);
        HOST_CS         : in    std_logic;
        HOST_RW         : in    std_logic;
 

The host interface is then handled in a single process that decodes the address bus and generates read/write strobes to four FIFOs (two read-only and two write-only, each read/write pair share an address) and two register (one read only and the other read/write).

The rest of the design is a DSP with a bunch of peripherals. The host sends and reads data through the FIFOs and gets status and interrupt information using the registers.

I _think_ the DSP side of the design will work as-is but I can't figure out how to convert the host interface to an axi-lite interface.

Any help/suggestions would be appreciated.