Genesys ZU 3EG Kernel Panic with x16 DRAM IC Bus width (per die)

[dyne21]

Hello,

 

The existing 4GB UDIMM has eight x8 DDR4 ICs. I want to replace it with 4GB UDIMM with four x16 DDR4 ICs. The DDR configuration was modified by the Vivado IP integrator accordingly. Relaunching SDK generated the updated codes. (psu_init*.*) The updated codes were copied to my petalinux folder for building bootable SD card. The SD boot was able to reach the u-boot prompt but kernel loading was failed as attached. Could you help me for this trouble?

 

Best Regards,

Jeff

x16_UDIMM_Kernel_panic.log

[elodg]

It does not look like the kernel panic is due to the new memory module. Although it is worth double-checking memory settings in Vivado for correctness, the kernel panic seems to appear late in the boot process, memory being exercised a lot before it. The stack dump localizes the issue in the i2c driver probe function. Please check the following Xilinx forum post with similar issue: https://support.xilinx.com/s/question/0D52E00006hpluwSAA/ultrascale-kernel-panic?language=en_US.

It seems that you are starting from our OOB project (https://github.com/Digilent/Genesys-ZU/tree/3eg/oob/master), although using an older version, 2019.1. Make sure that you are exporting the xsa from Vivado with bitstream and importing to Petalinux with the proper flow (petalinux-config --get-hw-description). Double-check the addresses in "Address Editor" in Vivado and the generated device tree (./components/yocto/layers/meta-xilinx-tools/recipes-bsp/device-tree/files/pl.dtsi).

To test your memory module you could also try the latest OOB image, which has dynamic DDR4 initialization done by FSBL during boot, so no Vivado changes are needed to accommodate different memory topologies. Follow the steps in https://digilent.com/reference/programmable-logic/genesys-zu/getting-started#getting_the_out-of-box_image. This image should work both with the bundled and any other supported DDR4 module.

 

[JColvin]

Hi @dyne21,

I have reached out to another engineer more experienced with the Genesys ZU 3EG about this question.

I know from the memory section of the reference manual, https://digilent.com/reference/programmable-logic/genesys-zu/reference-manual#main_memory, that there is some dynamic DDR initialization code that is used to configure the memory controller at runtime, though I do not personally know if that is the issue that you are running into here.

Thanks,
JColvin

[dyne21]

Hi Elodg,

 

Thank you. The latest OOB image works fine with both x8 and x16 DDR4 devices. Btw, what does dynamic initialization mean? 

 

Best Regards,

Jeff

[elodg]

What the BIOS too does during a PC boot: reading out the memory module characteristics via SPD and configuring the memory controller accordingly.