Cora Z7-07s and Xilinx system generator (for Simulink) compilation error

[Sammyy1132]

Hi, 

I was wondering, is there a way I can do hwcosim (JTAG) compilation through the Xlinix's system generator in Simulink using the Zynq-07s. The hwcosim token is not highlighted. I tried Vivado 2021 and model composer but had to drop down back to 2016.4 because that's when it last compiled, synthesized and implemented on a Zedboard using hwcosim. 

I tried HDL Netlist and IP Catalog compilations but to no avail. (that's another issue for another time). 

[JColvin]

Hi @Sammyy1132,

Digilent has not worked with Xilinx's system generator and Simulink, so we won't be able to offer much in terms of support for using that design flow. Either Xilinx or Mathworks would be able to give you more accurate information on the best way to debug and support this design flow.

Thanks,
JColvin