Zybo Z7 USB UART BRIDGE (SERIAL PORT)

[Sanket]

Hello All, 
I am new to FPGA field, I am using Vivado to program my fpga. I have succesfully programmed the zybo z7 fpga with basic logic gates and I was able to control inputs using switches and push buttons present on board.

My next aim is to program  " An 2 input AND gate and control the inputs from my PC"

1) Is this possible to do using zybo z7 board? XC7Z020-1CLG400c

2)Is there any tutorial or link which describes steps for something similar need not to be exactly "and gate program"

3)Is any external connection required to achieve this?

It would be great assist if I would get some info about basic steps required to achieve the aim

Thank You

  

[zygot]

Unfortunately, for simple basic beginner's projects like yours, the ZYNQ architecture just gets in the way and makes such projects like yours more complicated.

For a "2 input AND gate" project you really don't need a PC connection. But when you want to control a more complicated design you will need a more complicated user interface. 

The easiest way to connect your board to a PC is the PS UART. But, for now, you really just want to create some logic and control that from a PC. The good news is that yes you can do that. For $15 or less you can buy a 3V compatible TTL USB UART cable or breakout board from either Sparkfun or Adafruit. You only need 2 pins on a PMOD connector and an HDL UART component to achieve your aim. In this case the ARM cores are idle an not involved. No ARM software design. The best way to do the design is with VHDL or Verilog.

At some point you will want the ZYNQ PS to communicate with a design in the PL. For high speed data transfer you need AXI slave or master components in the PL. This is for more advanced developers if you want to have an all HDL PL design. The easy way around that is to use a board design that uses some of the various AXI IP provided for free with Vivado. I prefer to have Vivado create an HDL wrapper for the board design and then instantiate the wrapper in my own toplevel HDL entity. I tend to use the least amount of AXI IP possible for a lot of reasons. The board design flow can be quick and easy, or just limiting and frustrating; it ll depends on what you are trying to accomplish. I only use the board design flow for ARM based FPGA project, and then use the minimal amount of Xilinx board design IP as possible.

There's an even easier way to write PS code to read and write registers in the PL by muxing the unused PS UART to the EMIO that connects to the PL directly. As a matter of fact I just happen to be working on a demo to do just that. I can write an addressable  32-bit register in the PL and read back the new register value in less than 10 us. I can also read an addressable 32-bit register in the PL in under 6 us. All of this by using the PS UART registers, just like I'd do for a micro-controller. If you want to have faster access, then you can just address smaller register sizes like 8 bits. Hopefully, I'll have the demo in shape to post within the week. While this method isn't good for high speed data transfers between the PS and PL logic, it certainly works fine enough for a project like yours. It's also a nice way to view PL logic states for debugging purposes... potentially even better than the Xilinx ILA and VIO IP.

It's quite possible to using one PS UART to connect to a PC and the second one to connect to the logic at a much higher data rate. Actually, a lot of nice things align nicely with this method for ZYNQ. I've been using a similar, but slower and more complicated scheme for years as a debugging aid for non-processor FPGA designs.

There's generally more than one way to do things. I generally prefer the simpler way, when it's available and gets the job done.

Edited December 14, 2021 by zygot

[Sanket]

Thank you very much for the detailed response, I will try to execute steps mentioned by you, additionally I have few questions

1)Yes, " And gate project" was the example to explain my aim easier way, eventually the plan is to get a more complex stuff on fpga

2)Previously, all the approaches which I was getting was as follow, a) build a schematic b)build a hdl wrapper c)export d)code it in vitis e)communicate using serial port terminal by selecting proper baud rates. Is this one of the approach? Is yes can you elaborate this process 

3)Alternately, is this whole process possible with usb instead of UART?
 

[zygot]

Wait a couple of days for me to post a demo. I'm pretty close to having something suitable to post.

Technically, for FPGA boards the UART is a USB device. The days when RS-232 serial ports on PCs and development boards were present are long gone. At low data rates one might be able to ignore this fact. At higher data rates then practical uses for UARTs via USB become more noticeable. Some of Digilent's boards support 8-bit parallel USB connectivity for faster data rates. This requires additional PC software development as the USB connections are no longer enumerated as COM devices and (to a degree) shields the user from the details of controlling the data transfers.

[zygot]

Just for you ( and a whole lot of other people ): https://forum.digilentinc.com/topic/22512-manipulate-pl-logic-using-ps-registers/

 

[Sanket]

Thank You very much for the update, I will go through the content. I will inform you if I need more information. Thank You again

[zygot]

Though I posted the demo as a reply to your questions, you happen to be one of the folks who will have to port the VHDL code to your board. Sorry, but I don't provide demos or code for boards that I don't have access to and can validate. This shouldn't be too difficult to do. Just ask if there are problems as the dialog will be helpful to others following your steps.

I realize that the VHDL code has an ILA that I failed to cover in the instructions. Not a big deal. You can comment the ILA instantiation out or just create one. The code should be sufficient to guide this.

Please post questions regarding the demo to where you found it.

It's not always rewarding to answer questions to this forum, but every once in while a question spurs sparks an idea that I just have to work on. Thanks for that.