Zybo and Vitisi 2021.2 - slow hardware launch

[etnapoli]

I am working on Windows 10 and  Vitis 2021.2

I have the Hello world application runnning on Zybo (not Z7 version) Digilent board.

The HW is quite simple and is composed by the PS with GPIO, UART.

.elf size is 173kB

When I build the application is behaving normal. Build time 7s

Than I click on 'run on hardware' and wait.

1) starts program device after 45s

2) still launching system debugger 66% at 2min

3) it is at 69% after 4min 15s

4) it is at 81%  after 6min

5) finished after 6min 27s.

This is extremely slow and was not like that with zedboard and vivado 2021.1.

 

This is way too slow. I found a user that says this is a problem with the hw_server in version 2021.2

Is there anything I can do to solve the issue?

Thx.

[thinkthinkthink]

Used to happen for me as well, don't remember what fixed it, either ending the hw_server with Task Manager in Windows or restarting my PC. If you really want your board to program as fast as possible you can increase JTAG frequency to 30MHz in Vivado Hardware Manager. On kintex-7 and zynq ultrascale+ or above you'll see longer programming times since .bit files and etc. are bigger in size even on maximum JTAG frequency.

 

 

The only problem with increasing JTAG frequency is if you have any ILAs in your design you should make sure that the clock at which those ILAs are running is at least 2.5 times higher than JTAG frequency according to Xilinx.

Edited December 6, 2021 by thinkthinkthink

[etnapoli]

1 hour ago, thinkthinkthink said:

Used to happen for me as well, don't remember what fixed it, either ending the hw_server with Task Manager in Windows or restarting my PC. If you really want your board to program as fast as possible you can increase JTAG frequency to 30MHz in Vivado Hardware Manager. On kintex-7 and zynq ultrascale+ or above you'll see longer programming times since .bit files and etc. are bigger in size even on maximum JTAG frequency.

 

 

The only problem with increasing JTAG frequency is if you have any ILAs in your design you should make sure that the clock at which those ILAs are running is at least 2.5 times higher than JTAG frequency according to Xilinx.

Restarting the hw_server did not help.

However, restarting the notebook solved the issue. Thnk you for your help, who knows what was blocking Vitis.

By the way, how to increase the JTAG frequency in Vitis? The procedure you showed seems to be for Vivado.

[JColvin]

Hi @etnapoli,

Xilinx has some documentation on how to do this though the Target Connections button here: https://docs.xilinx.com/r/en-US/ug1400-vitis-embedded/Target-Connections. Effectively, you can click on the Target Connections button, right-click and view the Local connection under Hardware Server, Open the Advanced Tab, and select the name dropdown itself, upon which the Frequency button will become available so you can change the JTAG frequency from the default of 15 MHz.

Thanks,
JColvin

[elodg]

2021.1 seems to be working fine. Try that.