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Refresh of the FPGA Serial Accelerometer Tester

Tim S.

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Hi there.

Last year I posted on GitHub two projects that implement communication with the Pmod ACL2, targeting the Arty-A7-100 and Zynq-Z7-20 respectively. The past two months I've updated these projects to the Xilinx Vivado 2021.2 with TCL scripts version controlled for recreation of the project and block diagrams. You can find the design refresh at:




Note that there are five example Xilinx Vivado/Vitis projects that implement the same function:

- all SystemVerilog RTL

- all Verilog RTL

- all VHDL RTL

- Xilinx MicroBlaze system

- Xilinx Zynq-7000 system


Tim S.

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