Refresh of the FPGA Serial Accelerometer Tester

[Tim S.]

Hi there.

Last year I posted on GitHub two projects that implement communication with the Pmod ACL2, targeting the Arty-A7-100 and Zynq-Z7-20 respectively. The past two months I've updated these projects to the Xilinx Vivado 2021.2 with TCL scripts version controlled for recreation of the project and block diagrams. You can find the design refresh at:

https://timothystotts.github.io/2021/11/26/refresh-of-the-fpga-accelerometer-tester.html

and

https://github.com/timothystotts/fpga-serial-acl-tester-3/

Note that there are five example Xilinx Vivado/Vitis projects that implement the same function:

- all SystemVerilog RTL

- all Verilog RTL

- all VHDL RTL

- Xilinx MicroBlaze system

- Xilinx Zynq-7000 system

Regards,

Tim S.

[Tim S.]

At this time, support for the Arty-S7-25 has been added to three of the four Arty-A7-100 projects.

- all SystemVerilog RTL

- all Verilog RTL

- all VHDL RTL

 

[Ardelle Froeliger]

What an interesting sharing!

[Tim S.]

A MicroBlaze example for the Arty S7-25 has been added to the project. Support for Arty S7-25 is now as complete as support for the Arty A7-100.

EDIT:

A blog post on the updated project can be found at:

https://timothystotts.github.io/2022/06/12/fpga-accelerometer-tester-on-the-arty-s7-25.html

Edited June 12, 2022 by Tim S.