Differential outputs on Arty-A7 board with TMDS

[qamesh]

Hello,
Hi, I am experimenting with differential outputs on the Arty A7. For this, I am using the 100MHz clock and have instantiated an ODDR then OBUFDS -- . I Have also looked through the 7-series Select-IO Resources User Guide and the only  differential I/O at 3.3V is  TMDS_33 IOStandard.

ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("SYNC")
)ODDR_CLKADC(
.Q(buff_local),
.C(buff_in),
.CE(1'b1),
.D1(1'b1),
.D2(1'b0),
.R(1'b0),
.S(1'b0)
);

OBUFDS #(
.IOSTANDARD("TMDS_33") // Specify the input I/O standard
)OBUFDS_inst (
.O(buff_out_p), // Diff_p output (connect directly to top-level port)
.OB(buff_out_n), // Diff_n output (connect directly to top-level port)
.I(buff_local) // Buffer input
);

The .xdc file has the following --

## Pmod Header JB
set_property -dict { PACKAGE_PIN E15 IOSTANDARD TMDS_33 } [get_ports { buff_out_p }];
set_property -dict { PACKAGE_PIN E16 IOSTANDARD TMDS_33 } [get_ports { buff_out_n }];
Pins E15/E16 are HR I/O banks [JB1/2] and they should work fine.

Synthesis & implementation are fine and I can generate a bitstream, but I see no output on these pins (just 0v)
I also tried to connect a termination resistor of 50 ohm pulled up to 3.3 V as recommended for FP_3.3_50 [OFF chip termination]. but it gives nothing...can anyone help me in this?

Edited November 12, 2021 by qamesh
grammar mistake

[zygot]

I don't see anything wrong with what you've presented, in terms of using the IOSTANDARD. You are correct that TMDS_33 is the only available differential signalling for your board.

You might try starting off with an SDR output instead of a DDR output first. Your ODDR primitive should be a clock and dc balanced but perhaps isn't the best choice. Anyway, try connecting whatever is driving the _p side of the differential obuf with a single-ended obuf driving a different pin on the same PMOD as a sanity check.

It's a good idea to understand what TMDS is. It might be interesting to use a shift register that repeats a word as your data source.

Edited November 12, 2021 by zygot

[asmi]

You need to have external 50 Ohm pullups to 3.3V for TMDS to work as it's a current driver, but it looks like your problem is elsewhere in the code. Have you tried running a simulation to check that it works properly before you went for the hardware?

[qamesh]

On 8/22/2016 at 9:07 PM, D@n said:

I also connected this 50 ohm resistor to each terminal (P terminal  and N terminal ) exactly as it looks in the attached photo , but I was not able to see anything on the oscilloscope . I think it is not a problem in the code itself. The simulation shows that there is an output signal.

 

[asmi]

At this point I can only offer any help if you can publish the full project with all sources, as the problem can be anywhere.

[qamesh]

@asmiThank you for the offer. 

I went with the project as simple as possible , where I only take a clk signal from a Clock Wizard and route it out as a differential output but even this didn't help. The other module top_led_test is just a counter that I check the status of the board through it by connecting it to one of the leds

 

top.vhd top_led_test.v

Edited November 17, 2021 by qamesh

[asmi]

I've verified your code in hardware with oscilloscope (I don't have A7, so I used my homemade Spartan-7 board, but it should be OK as all 7 series FPGA use mostly the same HW blocks) - it works just fine with external 56 Ohm (the closest to 50 Ohm through-holes I had laying around) pullups to +3V3. I got about 1.3 Vp-p on both outputs (40 and 20 MHz). Due to time constraints, I've only checked _p lines, but I'm sure _n lines work too. So look for errors in your external hardware/measurement setup. Use AC-coupled mode on a scope, connect scope's ground to the board's ground, and check that your resistors are wired properly.

Edited November 19, 2021 by asmi

[elodg]

Those are the correct primitives to use and 50ohm termination is required. Signals _P and _N should typically be swinging between 3.3V and 3.3V-0.5V. Differential swing between +0.5V and -0.5V. Vdiff_pp = 1V.

I am thinking you might be looking at the wrong pin with the scope. Connect the ODDR output to a secondary OBUF (LVCMOS33) to debug this further. Open the  implementated design and confirm placement.