[ZYBO Z] I2S Transmitter sdata_out stuck to 0

[gian.deriu]

Hello, I'm trying to send an audio sample to the Audio Coded in the Zybo Z7 board. To do this I'm using the I2S Transmitter.

 

The AXI stream port is connected to an AXI Stream FIFO. Using the ILA debugger I can see that some data is sent to the transmitter from the FIFO (the valid wire becomes high) but sdata_0_out is stuck to 0. It never changes.

 

I've enabled the IP following the steps in the Programming Sequence paragraph of the white paper (pg308-i2s).

I think I'm missing something but what?

 

Thank you for your help.

Gianfranco

[JColvin]

Hi @gian.deriu,

I don't know which white paper you are referring to, but Digilent does use the Audio Codec on the Zybo Z7 in it's DMA Audio Demo which is available in the Example Projects section of it's Resource Center: https://digilent.com/reference/programmable-logic/zybo-z7/start#example_projects, which would let you see how we handled the various clocks.

This forum thread may be of help to you as well: https://forum.digilentinc.com/topic/21789-pmodi2s2-arty-z7-10/?sortby=date.

Let me know if you have any questions.

Thanks,
JColvin

[gian.deriu]

Hi JColvin, thank you for you answer.

I prefer to not use the DMA to access the audio data. What the Demo does is to read a chunk of samples and to write them back to the transmitter using the DMA for both operations. I want to manage the samples real-time using read-write operations.

I found a library in the Digilent Repository https://github.com/Digilent/vivado-library which includes the module https://github.com/Digilent/vivado-library/tree/master/ip/axi_i2s_adi_1.2 that solved my problem. To read and write samples I used an AXI Stream FIFO. I attach my design for other people looking for a similar solution (the design is more complex than the strictly necessary. The FIR compiler IP is not used).

Best regards,

Gianfranco

i2s_adi_design.pdf

Edited November 17, 2021 by gian.deriu