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4PCam IIC configuration problem


Nik

Question

Hello,

I am following digilent's ZedBoard 4Pcam FMC Adapter Demo project. But I need your help to understand some of the code line.

Could someone help me to figure out in the following code lines? This following code has been taken from main.cc. 

/* main.cc */

		.....
        //Constructing OV5640 objects in dynamic storage vs. automatic makes
		//ignoring cameras with init exceptions possible
		//Since the power enable signals is shared between all FMC Pcam Adapter ports,
		//cam_a will be the only one controlling it through the gpio_driver.
		try
		{
			muxch_a_ptr = std::make_unique<TCA9546>(iic_driver, 0, 1 << 0);
			cam_a_ptr = std::make_unique<OV5640>(*muxch_a_ptr, nopgpio);
		} catch (std::runtime_error const& e)
		{
			VERBOSE("Camera on port A did not initialize correctly: %s", e.what());
		}
        .....

When I open TCA9546.h. I have noticed following lines of code

	/**
	 *
	 * @param iic is the underlying I2C_Client driver to-be-wrapped
	 * @param a_pin specifies the mux hardware address pins A2-A0 on its 3 LSB
	 * @param channel_mask should have the bit(s) corresponding to the
	 * addressed channel(s) set to 1.
	 */
	TCA9546(I2C_Client& iic, uint8_t a_pin, uint8_t channel_mask) :
		iic_(iic), channel_mask_(channel_mask)
	{
		dev_address_ &= ~0x07;
		dev_address_ |=(a_pin & 0x07);
		reset();
	}

From above codes, I need your help to understand that how these codes are working to access PCam A in ZedBoard 4PCam FMC Adapter. What is happening here?

Thanks !

 

Kind Regards,

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Is anybody there? 

I want to know how four Pcams addresses are set in  ZedBoard 4Pcam FMC Adapter Demo project.

How  channel_masking is working and what is the value of a_pin?

 

I am trying to write a custom code for accessing and configuring the the four pcams but unable to do so.

I need your help.

 

Thanks,

Edited by Nik
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For the Genesys 2 FMC Pcam Adapter Demo I rewrote everything in C so it should be easier to understand. 

The a_pin parameter refers to those address lines (A0, A1, A2) on the I2C mux IC that's on the FMC Pam Adapter. As you can see the A2 line is already tied to GND so all that's left are A0(GA1) and A1(GA0) which come from the FMC connector. For those you have to check what they are tied to on the FMC connector that's on the Zedboard.

image.png.47e38a1cb54edbc32dac84199fc57705.png

image.png.141821c8c50354766423bc44585ac390.png

image.thumb.png.b4ff14fb1795113a76b0583ead53d59f.png

As you can see from the schematic, on the Zedboard the FMC pins corresponding to A1(GA0) and A0(GA1) are tied to GND.

So that makes the values of A0, A1, A2 to be 000, which makes a_pin be equal to 0 (or 0x00 in hex).

Basically, what you have to do is first address the I2C mux at address (0xE0 >> 1), tell it which channel to open (0, 1, 2, or 3) and then config your pcams through I2C at the (0x78 >> 1) address.  

 

Edited by thinkthinkthink
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Thank you. It helped me a lot.

But I am having little problem in IIC data writing. The program control stuck infinitely in the following code.

 

while ((!TransmitComplete && !slave_nack_flag_)|| (XIic_IsIicBusy(IicInstance) == TRUE));

 

Thanks,

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13 minutes ago, Nik said:

Thank you. It helped me a lot.

But I am having little problem in IIC data writing. The program control stuck infinitely in the following code.

 


while ((!TransmitComplete && !slave_nack_flag_)|| (XIic_IsIicBusy(IicInstance) == TRUE));

 

Thanks,

Which board are you running that on, Zedboard or Genesys 2 ? Did you just copy and paste the code from the Genesys 2 vitis project to your Zedboard vitis workspace ? The Zed project uses the PS_IIC i2c controller that's inside the ZYNQ processing system while the Genesys 2 one uses an AXI_IIC IP with SCL frequency set to 400kHz. There's a lot of driver differences between the two i2c controllers.

 

Why your processor is stuck on that line of code is because you're either not getting an ACK from your i2c slave and you're not getting a NACK either somehow, or maybe because the i2c bus is busy. What to do in this situation is to put some breakpoints in the Status and/or Send Handlers to see what happens with those flags. Another thing to do is to check with an ILA what happens with the SDA and SCL lines.

Right-click on the IIC line and select Debug.

image.png.5036a14bfd08aeb20082a6ca024bf13c.png

Then click on the huge horizontal green bar that says Run Connection Automation, once a new window pops up you can choose a clock on which that ILA will run, I recommend the clock output from the ZYNQ and then press Ok.

image.thumb.png.a2cb07fb14f2758149e5ed74e62bf242.png

Double click on the ILA IP and increase Sample Data Depth to as much as your design allows you (your bitstream might fails a couple of times until you get the right value, it's dependent on available BRAM so yeah...) and make sure to check the Capture Control box then press Ok.

image.png.f10dded46950ca7fc717e0b564b61822.png

Validate design and Generate Bitstream.

After updating hardware platform and rebuilding the entire vitis workspace (hardware platform + application project) run the project in in Debug mode, before going through the code step by step you should go back to Vivado, open the Hardware Manager tab and connect to your board then an ILA window should open as well.

Change Capture Mode to BASIC and in the Capture Setup tab add scl_i and sda_i signals. Also make sure to set capture condition to 'Global OR'.

image.png.6555b90207b774690ea0da5b875eeddb.png

image.png.ab128c01bcf220951b2824a013d12e2c.png

image.png.a227f07ebf05a42088eefebf32b409fe.png

Run trigger for this ILA core and see what happens when you go through the code step by step.

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Hi !

Thank you for the response. I solved the issue by using the interrupt handler. This time PCam is fully configured. However, I am not getting the data from MIPI IP. The TVALID signal is always LOW. Note that I am using Xilinx's MIPI CSI-2 RX Subsystem. What can be the issue here?

Thanks !

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On 12/1/2021 at 4:29 PM, Nik said:

Hi !

Thank you for the response. I solved the issue by using the interrupt handler. This time PCam is fully configured. However, I am not getting the data from MIPI IP. The TVALID signal is always LOW. Note that I am using Xilinx's MIPI CSI-2 RX Subsystem. What can be the issue here?

Thanks !

Hi !

I switched back to Digilent MIPI IPs, but does not seem to work. I used same configuration code provided in the reference design. Is there any way to debug MIPI IP. I used ILA and found no streaming of data. I am using vivado 2019.1.

 

Thanks,

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What development board are you working on and is your block design the same as in the FMC Pcam Adapter Demos ? Is the VADJ of your board set correctly to 2.5 V ? While debugging in SDK/Vitis is your processor getting stuck on a specific line most of the time ? How many Pcams do you have connected to the FMC Pcam Adapter ? Do the ribbon cables of the Pcams look ok ? Have you connected the Pcams correctly, are the ribbon cables inserted fully and tightened ?

This project is fairly complex and so many things can go wrong with it. The configuration code shouldn't have any issues so I'm suspecting there's something wrong with your hardware unfortunately.

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