Confusing phenomenon when verifying PmodBT2 in Vivado 2018.3 and SDK2018.3

[HomaGOD]

When building microblaze in SDK, it prompts that some parameters are undefined, especially those related to axi_uartlite.(Does that be related to not adding )

For example, #define SYS_UART_DEVICE_ID      XPAR_AXI_UARTLITE_0_DEVICE_ID can not be found during executing. 

 

 

[HomaGOD]

This is the initial error when I re-install vivado2015.3 and re-build microblaze.

Still, same error occur, which makes me collapsed. 

Having tried numerous ways, they ALL turn to fail.

Wish your help, all engineers and professionals.

 

[thinkthinkthink]

Have you looked in xparameters.h for the correct definition of your uart's DEVICE ID ?

[HomaGOD]

3 hours ago, thinkthinkthink said:

Have you looked in xparameters.h for the correct definition of your uart's DEVICE ID ?

I looked up to it. The error finally is resolved when I add axi_uartlite IP to board design diagram. 

However, when I run the applicaiton project as "Launch on Hardware", Recv data displays all zero in HEX and space in ASCII on UartAssist as follows.

 

 

The correct situation should be that Recv HEX displays "Initialized PmodBT2 Demo Received data will be echoed here, type to send data". It seems that FPGA cannot send data to PC. How should I find where the problems exist?

Thank you very much.

HomaGOD

 

The next screenshot display the running info when I run as Hardware, which I think might help you judge the porblem.

Edited November 2, 2021 by HomaGOD

[thinkthinkthink]

The PmodBT2 IP already contains an UART IP inside it no need to add another one in your block design, you just need to look in the xparameters.h header file for the correct DEVICE ID of that UART.

[HomaGOD]

6 hours ago, thinkthinkthink said:

The PmodBT2 IP already contains an UART IP inside it no need to add another one in your block design, you just need to look in the xparameters.h header file for the correct DEVICE ID of that UART.

Strange is that I do not find the DEVICE ID in the xparameters.h, which confuses me a lot.

[Ana-Maria Balas]

@HomaGOD,

Could you post a screencapture of your whole block design from Vivado? Then screen capture from the Adress Editor tab?

[HomaGOD]

17 hours ago, Ana-Maria Balas said:

@HomaGOD,

Could you post a screencapture of your whole block design from Vivado? Then screen capture from the Adress Editor tab?

Thanks for your reply and sorry for the late reply.

Next is the whole block design from Vivado.

 

This figure is screen capture from the Address Editor tab and .hdf file read in SDK.

 

For convenience, I want to upload the whole project file created in vivado2017.4. That is because that the tool can't find the Microblaze GCC like the following screen capture. But there is a limit of file size, is there any other alternative?

 

[thinkthinkthink]

Go to your hardware platform in vitis and double click on platform.spr, once that opens click on the Modify BSP Settings... button.

A new window will popup and then go to standalone under the Overview dropdown. Make sure that both stdin and stdout have their Value field set to axi_uartlite_0 (or whatever name your axi uartlite ip that you added later has). If you had to change them then don't forget to rebuild the whole workspace (meaning both the hardware platform and the application project).

I don't get any of the errors you get while trying to create a project like yours, except that Vitis can't create an .elf file and my theory, just like James Colvin has told you, is that unfortunately the Basys3 does not have sufficient BRAM and no RAM to run applications like this one.

Edited November 4, 2021 by thinkthinkthink

[HomaGOD]

On 11/4/2021 at 4:56 PM, thinkthinkthink said:

Go to your hardware platform in vitis and double click on platform.spr, once that opens click on the Modify BSP Settings... button.

A new window will popup and then go to standalone under the Overview dropdown. Make sure that both stdin and stdout have their Value field set to axi_uartlite_0 (or whatever name your axi uartlite ip that you added later has). If you had to change them then don't forget to rebuild the whole workspace (meaning both the hardware platform and the application project).

I don't get any of the errors you get while trying to create a project like yours, except that Vitis can't create an .elf file and my theory, just like James Colvin has told you, is that unfortunately the Basys3 does not have sufficient BRAM and no RAM to run applications like this one.

 

Many thanks to your warm reply and sorry for my late reply.

First, Confusing is that when I clicks on the Modify BSP Settings... button, the value of both stdin and stdout is NONE ratherthan axi_uartlite_0. Would you please be so kind to give me some guidance.

Second, I noticed that there is an error in your screen capture of kojima_system tab as is marked in the following figrue. Could you be please provide a figure with that error if convenient? Thank you. 

 

 

Besides, I have confusion about the theory you and James Colvin have told me.

I have looked up to the user manual of Basys3, which says it has 50 BRAM, with every BRAM's scale is 36kb, thus Basys3 can provide 225KB(50*36kb/8) size of BRAM. Meantime, I open the implemented design and report the utilization of the whole board design. It prompts that it only consuming 8% of the BRAM.

Therefore, I do not know how to judge whether Basys3 has sufficient BRAM to run applications like BlueTooth transmission. In other words, what is the common basis of judgment?

 

Finally, what I want to add is that this link http://digilent.com.cn/community/222.html#top gives a proof that Basys3 can run demo application (print some info). 

But the above design's demo program is unlike main.c in directory xxx\drivers\PmodBT2_v1_0\examples, maybe different versions of example program require different BRAM? Of course, this is only my personal guess.

Wish your reply, when convenient.

 

Thanks,

HomaGOD

 

Edited November 7, 2021 by HomaGOD
add some info

[thinkthinkthink]

This is the error I was getting, but look at what it says when I scroll to the right. BRAM has overflowed.

 

To change stdin and stdout you can just choose from the dropdown list in their Value field.

[HomaGOD]

23 hours ago, thinkthinkthink said:

This is the error I was getting, but look at what it says when I scroll to the right. BRAM has overflowed.

 

To change stdin and stdout you can just choose from the dropdown list in their Value field.

 

Thanks for your warm reply!

Strange is that I can not set the value of stdin and stdout as axi_uartlite_0. The dropdown list of of Value field is none like this. I do not know what went wrong.

 

 

Secondly, the error you presented really makes sense. But, strange is that the results of my building platform and application are quite different from yours.

Everytime when I build application, it always prompts fatal error: xuartlite.h: No such file or directory, which confuses me a lot.

 

 

I attach the .xsa file, would you please spare time to check what went wrong if convenient?

 

Thanks a lot.

HomaGOD.

 

BT2_design_wrapper.xsa

[thinkthinkthink]

Do you even have an AXI UartLite IP in your block design ? If not you have to add it, re-Generate Bitstream and export hardware, then go to Vitis, right click on your hardware platform and select Update Hardware Specification.  

[HomaGOD]

4 hours ago, thinkthinkthink said:

Do you even have an AXI UartLite IP in your block design ? If not you have to add it, re-Generate Bitstream and export hardware, then go to Vitis, right click on your hardware platform and select Update Hardware Specification.  

 

I do not add an AXI UartLite IP in my block design in that I remember a digilent engineer told me that there is already an UART ip in PmodBT2.

 

According to your hint, I right click on my hardware platform and select Update Hardware Specification, but it failed. The error info is as follows.

 

Edited November 9, 2021 by HomaGOD

[thinkthinkthink]

Well you need to add an axi uartlite to your block design cuz the uart inside PmodBT2 is for a different purpose.

[HomaGOD]

7 hours ago, thinkthinkthink said:

Well you need to add an axi uartlite to your block design cuz the uart inside PmodBT2 is for a different purpose.

Could you please give a more detailed description of the uart inside PmodBT2?

Then, I add an axi uartlite to my block design, re-generate bitstream and build the platform and application project.

But no error occurs, especially related to BRAM, which is shocking.

The next two screen-captures are console info after I build the application.

 

 

Still, sometimes after I build application project, it prompts that make: Nothing to be done for 'all'.

 

What is the difference between the two parts that the arrow points to in the next screen-capture? 

 

Thanks a lot in advance.

Wish your reply.

HomaGOD.

 

Edited November 9, 2021 by HomaGOD

[HomaGOD]

On 11/8/2021 at 3:43 PM, thinkthinkthink said:

This is the error I was getting, but look at what it says when I scroll to the right. BRAM has overflowed.

 

I just remember that your error about BRAM might should be related to the following settings. In my design, I set Local Memory optons as 32KB.

This might explain why I do not met with an error as yours.

 

 

 

[HomaGOD]

Excuse me, can any professional help me check the question?