Nexys-Video-dma-audio-demo cannot get audio data

[ffggt]

Hi Digilent's engineer,

When I use Digilent audio demo(https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-video-dma-audio-demo/start) I find that it dose not work at Vivado 2019.1/2018.3. The bitstream can be generated successfully, and the C file in Xilinx SDK runs well, but I find that it cannot get audio data, so recording can never be done, also I find that it can be run well at Xilinx Vivado 2019.2/2020.2 and VITIS 2019.2/2020.2, but I must use Vivado 2019.1 and Xilinx SDK because of Cortex M3 IP. I must find out why system dose not work at Vivado 2019.1 , but everything seems like no error here.

Thanks a lot!

Vivado 2019.1 and Xilinx SDK (not work)

Vivado 2020.2 and Vitis2020.2(work)

 

[JColvin]

Hi @ffggt,

I upgraded the 2018.2 release project from our Github (https://github.com/Digilent/Nexys-Video-DMA/releases) to 2019.1 Vivado/SDK but did not encounter any issues; I have heard previously that the audio demo had an issue where it was stuck recording continuously, but I wasn't able to replicate this.

I have attached my exported SDK file; all you will need to do is open up SDK, choose a location for the project to live in, on the main SDK screen select the "Import Project" option, and then select "Import archive file" and ensure all three boxes are selected. After that, you should be able to build the project.

You may have to adjust your run configurations (Run tab -> Run Configurations, System Debugger on Local, Target setup tab, Debug Type -- Standalone Application Debug) have the Reset entire system and Program FPGA boxes checked. But then you should just be able to program the FPGA from the Xilinx -> Program FPGA and then Launch the application on hardware and have it work correctly.

Let me know how this goes for you.

Thanks,
JColvin

NVideoDMAAudio-191SDK.zip