Issues Following the Digilent Pmod IPs in Vivado and Vitis Tutorial

[jcanalesv]

I'm following Digilent's PMOD IPs in Vivado and Vitis Tutorial, but I keep having problems building the project. I'm using CMOD A7 and the CLS PMOD display. The bitgen keeps complaining about pin planning errors. I've retraced my steps through the tutorial, but can't see where I'm having trouble. I've copied the file and an image of my block diagram. I've also tried allowing the bitstream creation with unspecified I/O standard values as the error message suggests by using the set_property... tcl command. Is it possible that this IP is not working properly? Thanks in advance for the help. Here's the full error I'm getting:

[DRC NSTD-1] Unspecified I/O Standard: 4 out of 12 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io.

[DRC UCIO-1] Unconstrained Logical Port: 4 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io.

 

CLS.xpr

[JColvin]

Hi @jcanalesv,

I'm guessing you are using a newer version of Vivado (2020.2)? This is a known issue for this later version of Vivado as mentioned in this thread, https://forum.digilentinc.com/topic/21585-pmodhygro-errors-in-vivado-20202/, though the IP should work as is in earlier versions of Vivado. (I'll have to check for the newest 2021.1 that was just release a couple of days ago).

I apologize for the inconvenience.

Thanks,
JColvin