PmodHygro Errors in Vivado 2020.2

[SCollins]

Using the Digilent PmodHygro IP in Vivado 2020.2 I am getting the following DRC errors.

[DRC NSTD-1] Unspecified I/O Standard: 6 out of 146 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin10_io, ja_pin1_io, ja_pin2_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io.

[DRC UCIO-1] Unconstrained Logical Port: 6 out of 146 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: ja_pin10_io, ja_pin1_io, ja_pin2_io, ja_pin7_io, ja_pin8_io, and ja_pin9_io.

Searching thru these forums I have seen similar results

with a suggested workaround

On 2/2/2021 at 5:54 PM, JColvin said:

Possibly. There is a potential work-around listed for the IP on our GitHub here: https://github.com/Digilent/vivado-library/issues/51, though this has not been fully tested beyond generating a bitstream.

I have tried the workaround with no success. :-(

Maybe I didn't apply the work around correctly or upgrade the updated IP correctly, I just don't know.

If anyone has any suggestions or if Digilent has upgraded the IP to work with Vivado 2020.2 or have plans to anytime soon I would like to know.

Thanks

[SCollins]

I was able to make more progress after checking that the IP was updated.

The workaround suggested previously changes the PMOD bottom row interface to none, so pins 7,8,9, and 10 are not giving me errors anymore.

I am now only getting errors on pins 1 and 2.

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 146 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ja_pin1_io, and ja_pin2_io.

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 146 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: ja_pin1_io, and ja_pin2_io.

The PmodHygro device only uses pins 3 and 4 for IIC communications. So pins 1 and 2 just pass thru the PMOD.

Can I work around this by bu not using JA for the board interface and using a custom interface and editing the master.xdc file?

If it is of any help I am trying to get the PmodHygro working on the Arty Z7-20 using Vivado 2020.2

Thanks

 

[JColvin]

Hi @SCollins,

Our Pmods have some issues with Vivado starting with 2020.2 where some optimizations (or non-existing optimizations, I'm not certain) have changed so the Pmod IPs/structure are not working as intended.

I asked another engineer more familiar with the Pmod IP internals and I think you might be able to use a custom interface or expand the Pmod interface and mark the pins you need as external, though I do not know if that will work. I know Digilent is wanting to get the Pmod IPs working on Vivado 2020.2, but the engineer who would normally be addressing this has been tasked other projects and they aren't certain how long it would take.

Thanks,
JColvin