What IOSTANDARD should I use for PMOD JXADC with VADJ 1.8V?

[Zzingoh]

Hi All,

 

I am trying to implement SPI interface and have been using PMOD JXADC. My host board requires 1.8V so I am using SET_VADJ and VADJ_EN for driving 1.8V. With this configuration, it works find with 15MHZ/25MHZ but sometime it doesn't work and from the logic analyzer, I am seeing data skew. 

Especially pins(spi_reserve1, spi_reserve2) from JXADC bottom row(_N pins), I am seeing the problems. 

 

1. what IOSTANDARD should I use? I am using LVCMOS18. Is that correct or can I use LVDS18?

## XADC Header
# 1.8V
set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS18 } [get_ports { spi_clk }]; #IO_L3P_T0_DQS_AD1P_15 Sch=xa_p[1]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets spi_clk_IBUF]
set_property -dict { PACKAGE_PIN H14   IOSTANDARD LVCMOS18 } [get_ports { spi_reset }]; #IO_L3N_T0_DQS_AD1N_15 Sch=xa_n[1]
set_property -dict { PACKAGE_PIN H13   IOSTANDARD LVCMOS18 } [get_ports { spi_cs }]; #IO_L1P_T0_AD0P_15 Sch=xa_p[2]
set_property -dict { PACKAGE_PIN G13   IOSTANDARD LVCMOS18 } [get_ports { spi_reserved1}]; #IO_L1N_T0_AD0N_15 Sch=xa_n[2]
set_property -dict { PACKAGE_PIN G15   IOSTANDARD LVCMOS18 } [get_ports { spi_miso }]; #IO_L2P_T0_AD8P_15 Sch=xa_p[3]
set_property -dict { PACKAGE_PIN G16   IOSTANDARD LVCMOS18 } [get_ports { interrupt}]; #IO_L2N_T0_AD8N_15 Sch=xa_n[3]
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS18 } [get_ports { spi_mosi }]; #IO_L5P_T0_AD9P_15 Sch=xa_p[4]
set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS18 } [get_ports { spi_reserved2 }]; #IO_L5N_T0_AD9N_15 Sch=xa_n[4]

 

2. According to reference manual, recommended usage is 2.5V, differential pairs, I am new to the this area so don't understand fully regarding the difference between single ended and differential. In my project,

2.1 should I use single-ended pins or differential pins? if differential is okay then a host SPI pins should support also differential pair?

2.2 PMOD JXADC support V1.8V?

2.3 Should I use FMC interface instead of JXADC?

 

Thanks you

Jin

 

Edited May 23, 2021 by Zzingoh
wording change

[JColvin]

Hi @Zzingoh,

I'm presuming you are asking about the Nexys Video. I've asked another engineer to take a look into this thread (they said they'll need to double check datasheets and various board values before they get back to you) though I do not know when they will get the opportunity to do so.

Thanks,
JColvin

[Zzingoh]

Thanks you for your support. 

 

Yes. My board is Nexys Video.

One more question, from the reference manual, there is miscellaneous XADC pins. Would you let us know how to use this?

Does it support 1.8V?

What PACKAGE_PIN should be used for UP and UN. I am seeing errors when I use as like below

[DRC NSTD-1] Unspecified I/O Standard: 2 out of 19 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: spi_clk_0, and spi_cs_0.
 

set_property -dict { PACKAGE_PIN L10   IOSTANDARD LVCMOS18 } [get_ports { spi_clk_0 }];
set_property -dict { PACKAGE_PIN M9    IOSTANDARD LVCMOS18 } [get_ports { spi_cs_0 }]; 

 

Thanks you

Edited May 25, 2021 by Zzingoh
add more info

[artvvb]

Hi @Zzingoh

 

The VP/VN signals are dedicated analog inputs and should not be used for your digital SPI signals. Descriptions of each of the analog-capable pins can be seen on page 16 of the XADC user guide (https://www.xilinx.com/support/documentation/user_guides/ug480_7Series_XADC.pdf).

Using differential signals requires you dedicate two package pins to each signal (you would have separate constraints for spi_clk_p and spi_clk_n, for example), and likely requires you to explicitly instantiate differential buffers in your design. The device on the other end of the connection would also need to be differential.

I'm not 100% certain, but it could be that you are starting to run into the speed limitations mentioned in the reference manual for the board.

 

Thanks,

Arthur

[Zzingoh]

Thank you @artvvb

 

I have a following question. In my design, I need to use 1.8V due to a host HW limitation. that's why I am using XADC with 1.8V.

Would you please recommend me what pins I should use for 1.8V? Pins in FMC? 

Are the pins the single ended?

 

Thanks,

Tommy

[artvvb]

@Zzingoh

It looks like this thread on the Xilinx forum may have more information on this topic:

https://forums.xilinx.com/t5/Processor-System-Design-and-AXI/FMC-single-ended-signal-routing/td-p/808012

Thanks,

Arthur