MarkSe Posted December 15, 2020 Share Posted December 15, 2020 I've been creating a small collection of useful modules like Timers, Counters, etc. as part of my learning of HDL. There are many great examples of Timers out there but I'm offering up my own as yet another option. The timer has a pre-scaler option that divides down the incoming clock signal. Both the timer bit resolution and pre-scaler size are configurable parameters. Here is the module declaration as an example. module timer_scaled #( parameter TIMER_BITS = 8, SCALER_BITS = 2 ) ( input clk, // clock input input rst, // async reset input en, // timer enable input [TIMER_BITS - 1 : 0] d_in, // timer start value, input [SCALER_BITS - 1 : 0] ps, // pre-scale factor output [TIMER_BITS - 1 : 0] q, // timer current value output tick // tick event raised when timer reaches zero ); The full design as well as a short description are available here. A link to the code on github is provided. D@n 1 Link to comment Share on other sites More sharing options...
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