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FPGA Timer With Pre-Scaler


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I've been creating a small collection of useful modules like Timers, Counters, etc. as part of my learning of HDL. There are many great examples of Timers out there but I'm offering up my own as yet another option.

The timer has a pre-scaler option that divides down the incoming clock signal. Both the timer bit resolution and pre-scaler size are configurable parameters. Here is the module declaration as an example.

module timer_scaled
        parameter TIMER_BITS = 8,
        SCALER_BITS = 2
    input clk,  // clock input
    input rst,  // async reset
    input en,   // timer enable
    input [TIMER_BITS - 1 : 0] d_in,  // timer start value,
    input [SCALER_BITS - 1 : 0] ps,   // pre-scale factor
    output [TIMER_BITS - 1 : 0] q,    // timer current value
    output tick                       // tick event raised when timer reaches zero

The full design as well as a short description are available here. A link to the code on github is provided.

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You even provide testbench examples, nice.

Before there was programmable logic we used counters, shift registers, adders, state machines and other simple constructs to do complex designs. Nothing has really changed. Some HDL beginners are intimidated by the scope of HDL source code but really most problems are solved with the clever use of those old simple constructs. Mastering those is a great way to start off an FPGA design career.

[edit] The preferable way to use the Digilent Project Vault is to post an archive containing the source and documentation so that the user doesn't have to follow a link to some other, perhaps less safe website. There are those who choose to use this forum as a means to attract new readers to their own website, and I guess that this is fine if the intention is to educate. Anyone blithely connecting to unknown links should be aware of the dangers involved. Digilent's website is well maintained and curated. Others may not be. Wordpress powered websites have been a target for malware purveyors for a long time. While I'm happy to see content directed at helping newbies develop their HDL skills I feel compelled to remind people to be safe.

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  • 3 weeks later...

Yes, I am a firm believer in testbench collateral.

And thank you, I can understand the sensibility around links vs. posted content. It is more a matter of effort than principal, meaning I am not against posting an archive. It was much simpler for me to post a link to existing content and documentation than to package up the material for sharing.

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