FPGA Pulse Width Modulation

[MarkSe]

I was looking for a nice and simple PWM generator that I could use as a an add-on peripheral for a uC design that I am exploring. A PWM is not very difficult, so I created what I am sure is yet another one. The bit resolution is a configurable parameter.

It is a good exercise as I am still improving my HDL skills. I have not yet added a pre-scaler, that may be next.

You can find a short description of the design here. A link to the code on github is provided.

[D@n]

@MarkSe,

Just a quick question on your test bench: Should the release from reset be synchronous with a positive edge of the clock?  I've seen a lot of weird behavior associated with non-blocking assignments, enough that I try to use blocking assignments for all signals that are supposed to be clock synchronous.

Dan

[MarkSe]

On 12/21/2020 at 6:16 AM, D@n said:

@MarkSe,

Just a quick question on your test bench: Should the release from reset be synchronous with a positive edge of the clock?  I've seen a lot of weird behavior associated with non-blocking assignments, enough that I try to use blocking assignments for all signals that are supposed to be clock synchronous.

Dan

Yes, as I understand it, the better form is to avoid a fully asynchronous reset. At the same time I find many examples in textbooks and around the web that use the pattern that I've shared. YMMV.