Pmod connector as serial output

[CVPeck]

Hello all,

I need a second serial output from my Arty to drive an Iridium modem (via RS232 level shifters).

I'm unclear how to connect the outputs from a second UART lite to the PMOD connector in Vivado. Adding the PMOD connector to the block diagram automatically adds a Pmod ACL 2. I have then connected the UART rx and tx lines to Pmod in and out ports. Is that correct? 

[CVPeck]

Follow up to this, 

Quote

[DRC UCIO-1] Unconstrained Logical Port: 2 out of 78 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: jd_pin3_i, and jd_pin4_o.

So I'm guessing that even if the hookup is correct, then I have do something else to physically constrain the ports

[JColvin]

Hi @CVPeck,

Are you wanting to do a loopback from from the AXI Uartlite to a Pmod? Or just have a non-Pmod-specific UART output on a Pmod port?

Presuming it is the latter, what I would do would be to add the Pmod Bridge (both the 1.0 and 1.1 version will work) and then double-click on it to configure it as a UART bridge. You can then connect an AXI_uartlite to the UART_top_row and the connect an AXI_GPIO to the UART_GPIO_top_tow.

Alternatively, you can just add an AXI Uartlite and make the RX and TX pins external and configure those two external pins to be connected to whatever Pmod pin you wanted through the Arty's .xdc file.

Let me know if you have any questions about this.

Thanks,
JColvin

[CVPeck]

Thanks @JColvin, I’m actually trying to use the PMod RS232. It doesn’t come with any IP so I’m struggling to connect it up.

It’s being used to drive an iridium modem at RS232 voltages.

[CVPeck]

Thanks @JColvin for the guidance. It's now looking like this -

 

 

The idea being that the RS232 PMOD will be connected to the top row of JD. I believe it complies with the UART spec so I have selected that type for the JD top pins. I added an axe_uartlite to enable connection of the PMOD bridge to the axi bus. The tx and rx outputs from the UART connect to the PMOD bridge so hopefully these will connect to the appropriate pins on the top row of the PMOD on JD.

I'm still confused as to which pins to connect from the uart_lite_1 to the pmod_bridge. The PMOD RS232 has the following pinout

So I connected the uart_lite to out2_i and  out3_t. Is this correct?

Thanks,

Chris

 

 

[CVPeck]

The above design is still giving me unconstrained pin errors so something still not quite right -

Quote

[DRC UCIO-1] Unconstrained Logical Port: 3 out of 78 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined.  To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1].  NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run.  Problem ports: jd_pin3_o, jd_pin4_i, and jd_pin4_o.

 

design_1.tcl

[JColvin]

Hi @CVPeck,

Oh, the Pmod Bridge would not work as is for the Pmod RS232 because the RX and TX lines are on pins 3 & 4 rather than 2 & 3 like most of our UART Pmods and the Pmod Bridge IP. Digilent used to have a Pmod RS232X that put the RX and TX lines on pins 2 & 3, but that product was discontinued a number of years ago, though I never found out why; I should probably bring that back up again.

The way you have your block design set up, you appear to be looping the Uartlite IP signals into the Pmod Bridge "outputs" so your signals aren't actually getting out of the board. I don't know your design requirements with regards to RTS and CTS, but you could just set the rx and tx signals on the Uartlite IP as external, like it is shown in the picture and then change the get_ports pin name for pins 3 and 4 of whatever Pmod port you plan on using to tx_0 and rx_0, respectively. I have attached a pdf of the block design I tried and was successfully able to generate a bitstream for. I didn't do any of the Vitis/SDK materials though.

Let me know if you have any questions.

Thanks,
JColvin

externalUartDesign.pdf

[CVPeck]

Thanks @JColvin, I’ll give that a go.