I am using an original ARTY board ver C. I have a microblaze with ethernet, memory, etc, which is a design that I have used on other projects. I now added a quad_axi_spi board component with SPI port J6. My code is based on the Xilinx \embeddedsw\XilinxProcessorIPLib\drivers\spi_v4_4\examples.
I can get the SPI to successfully transfer data in LOOPBACK mode but when I run without loopback, with a scope I do not see the SCLK move on pin 3 of SPI connector J6 at all. When I look inside the FPGA, it looks like the SCLK is routed to the correct pin (F1). The board file has the correct FPGA pins specified. I have used the SPI flash with bootloader in the past, but not including SPI flash yet in this design until I can make J6 SPI work. Ultimately I want to control an LMX2592 PLL chip. Ehternet and serial UART both work in this design.
Are there any examples or hints for using SPI on J6 with ARTY in this way? Am i doing something obviously wrong?
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davec
Hi,
I am using an original ARTY board ver C. I have a microblaze with ethernet, memory, etc, which is a design that I have used on other projects. I now added a quad_axi_spi board component with SPI port J6. My code is based on the Xilinx \embeddedsw\XilinxProcessorIPLib\drivers\spi_v4_4\examples.
I can get the SPI to successfully transfer data in LOOPBACK mode but when I run without loopback, with a scope I do not see the SCLK move on pin 3 of SPI connector J6 at all. When I look inside the FPGA, it looks like the SCLK is routed to the correct pin (F1). The board file has the correct FPGA pins specified. I have used the SPI flash with bootloader in the past, but not including SPI flash yet in this design until I can make J6 SPI work. Ultimately I want to control an LMX2592 PLL chip. Ehternet and serial UART both work in this design.
Are there any examples or hints for using SPI on J6 with ARTY in this way? Am i doing something obviously wrong?
Thanks
Dave
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