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davec

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  1. Has anyone ever had success bring sys_clk in on a different pin on the ARTY (other than E3)? I cannot get a complete route no matter what i do. It seems SOMETHING in the board file is always placing the MMCM in a clock region (X0Y1) different than the MRCC clock pin that I am trying to use. Clock_dedicated_route_false does not help.
  2. Thanks for your reply zygot. Vivado also says: "The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances. Clock Rule: rule_mmcm_bufg Status: PASS Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device hopper_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2 and hopper_i/clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y21" Something is telling the placer to put the MMCM in X1Y2, which is where the original clk pin was (E3). I constrained the clk to be on pin P17, which should be in X0Y1. Is this from a board file, or maybe there is no MMCM in X0Y1 region of this chip? It routed with CLOCK_DEDICATED_ROUTE BACKBONE and CLOCK_DEDICATED_ROUTE FALSE constraints on the clk_wiz. In the old days, I would pip hack the connection if the router would not, but these chips are too big for that. :^)
  3. Hi, How do I bring the clock in on a different pin? I have a working microblaze design on an Arty A7-100 board and need to provide my own external 100 MHz clock. When I define the clock pin in my constraints file, I get this error: "[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets hopper_i/clk_wiz_0/inst/clk_in1_hopper_clk_wiz_0_0] > hopper_i/clk_wiz_0/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X0Y76 hopper_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2 The above error could possibly be related to other connected instances. Following is a list of all the related clock rules and their respective instances. Clock Rule: rule_mmcm_bufg Status: PASS Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device hopper_i/clk_wiz_0/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y2 and hopper_i/clk_wiz_0/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y21" It seems the clock wizard is being placed from the board file in a location not compatible with my desired pin constraint (P17), even though I select "custom" in the clocking wizard IP for clock input, instead of board file. Do I need to draw a GCLK IOB in the block design, or some such? Thanks
  4. Hi Richard, I am having trouble getting this to work using your directions. When I worked with an Arty board, I figured this out and it would boot my SDK code from qspi flash. Now I'm using a CMOD A7 and my simple microblaze program works when tethered, but I can not get it to boot from qspi flash. Why do you first create the project with AXI Quad Standard mode, and then later constrain it to SPIx4? I have been going in circles with Vivado constantly telling me files are out of date and not finding .h files until I do a "clean". Maybe it is time to dump the CMOD and just use an Arduino for this project. I wish Digilent would describe a bootload procedure for the CMod-A7 that works. Too many differences from the example they show (example also uses DDR and MIG) which CMOD doesn't have. As far as the time delay, how can the SDK code run before the device configures? It has to configure in order to run the bootloader. Thanks
  5. This is more of an Vivado SDK question, but I am debugging microblaze code on a CMOD-A7 board. In debug mode, I can't figure out how to get my peripherals (axi-uartlite, axi_intc, etc) to appear in the register view- only the microblaze registers are showing up. In a similar design on an Arty board they all appear in the register view, both registers and peripherals. The peripherals work, I just can't view their register values. I'm running 2019.1 on windows because all my legacy code is there. Can't find any clue in the SDK doc. Thanks.
  6. Thank you, Arthur! I actually discovered this just before I read your email. When I realized I wasn't actually specifying the slave device, I punched it into the SPI_SSR during a breakpoint and that didn't work. When I saw someone's example that called XSpi_SetSlaveSelect, the clock (and select line) started to work. What threw me was that in the example, they run in loopback mode and they don't need to bother with setting the slave select. It was hard to find an example that used external pins (and not loopback). Next, I have to add a second SPI device, so I guess I need to add a constraint to specify which pin the new SS will come out on. Can I use a GPIO, or will there be a conflict?- I am never quite sure how Vivado reads the board file pin locations. Thanks again, Arthur. Dave
  7. Hi, I am using an original ARTY board ver C. I have a microblaze with ethernet, memory, etc, which is a design that I have used on other projects. I now added a quad_axi_spi board component with SPI port J6. My code is based on the Xilinx \embeddedsw\XilinxProcessorIPLib\drivers\spi_v4_4\examples. I can get the SPI to successfully transfer data in LOOPBACK mode but when I run without loopback, with a scope I do not see the SCLK move on pin 3 of SPI connector J6 at all. When I look inside the FPGA, it looks like the SCLK is routed to the correct pin (F1). The board file has the correct FPGA pins specified. I have used the SPI flash with bootloader in the past, but not including SPI flash yet in this design until I can make J6 SPI work. Ultimately I want to control an LMX2592 PLL chip. Ehternet and serial UART both work in this design. Are there any examples or hints for using SPI on J6 with ARTY in this way? Am i doing something obviously wrong? Thanks Dave
  8. Thanks much for board geometry.  Looking forward to using Arty.

    mulțumesc,

       Dave

     

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