Ethernet on ARTY with Linux

a.gamez · May 12, 2016

Hi!

I've implemented a Microblaze system on the ARTY board, which includes a Texas Instruments DP83848 PHY chip to manage ethernet communications.

Xilkernel and example program 'echo server' works wonderfully, so any hardware issue is discarded.

However, on linux (using both mainstream and xilinx' github repo), I can't get ethernetlite core to work. This is the info I can provide:

                axi_ethernetlite_0: ethernet@40e00000 {
                        compatible = "xlnx,xps-ethernetlite-1.00.a";
                        device_type = "network";
                        interrupt-parent = <&microblaze_0_axi_intc>;
                        interrupts = <1 0>;
                        reg = <0x40e00000 0x10000>;
                        xlnx,duplex = <0x1>;
                        xlnx,include-global-buffers = <0x1>;
                        xlnx,include-internal-loopback = <0x0>;
                        xlnx,include-mdio = <0x1>;
                        xlnx,rx-ping-pong = <0x1>;
                        xlnx,s-axi-id-width = <0x1>;
                        xlnx,tx-ping-pong = <0x1>;
                        xlnx,use-internal = <0x0>;
                        axi_ethernetlite_0_mdio: mdio {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                phy0: phy@0 {
                                        device_type = "ethernet-phy";
                                        reg = <0>;
                                };
                        };
                };

phy0 section was written by me, as it was not provided by dts creation utility for the SDK.

dmesg output:

xilinx_emaclite 40e00000.ethernet: Device Tree Probing                                                                                                                                                              
xilinx_emaclite 40e00000.ethernet: Failed to register mdio bus.                                                                                                                                                     
xilinx_emaclite 40e00000.ethernet: error registering MDIO bus                                                                                                                                                       
xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00                                                                                                                                             
xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF0140000, irq=2

Relevant kernel config:

CONFIG_NET_VENDOR_XILINX=y
CONFIG_XILINX_EMACLITE=y
CONFIG_PHYLIB=y
CONFIG_DP83848_PHY=y
CONFIG_XILINX_PHY=y

eth0 interface appears, and ifconfig eth0 192.168.1.222 doesn't produce any error. However, no other host on the network can reach the ARTY nor viceversa, not by ping, nor by poking at any random port.

Any ideas?

Thanks!

sbobrowicz · May 14, 2016

Hey, congrats on getting linux running on Arty! Have you documented this process anywhere?

Regarding your problem, I may not be of much help, as I haven't gotten Linux running on a microblaze in a very long time... One thing I did notice is that you are setting the PHY address as 0, but the address on the Arty is 1. Try the following device tree node for the PHY:

axi_ethernetlite_0_mdio: mdio {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                phy1: phy@1 {
                                        device_type = "ethernet-phy";
                                        reg = <1>;
                                };
                        };

a.gamez · May 17, 2016

I'm afraid that didn't work, exactly the same keeps happening. How do you know PHY address is 1? I haven't found any document that specifies it.

a.gamez · May 17, 2016

Hi again!

I've found this document which, at page 9, stablishes what DP83848 PHY addr is https://download.beckhoff.com/download/Document/io/ethercat-development-products/an_phy_selection_guidev2.3.pdf

You're definitely right that PHY address is 1, by that document. However, setting <reg> to 1 doesn't make any difference.

I've also tried several values, ranging from PHY addr 0 to 4, and 16 to 20 with no luck, always with the same result. There must be something I'm missing, but I don't know what is it...

I haven't any of this documented yet, but once I get this working I will surely do!

sbobrowicz · May 17, 2016

We also document the PHY address in the reference manual and schematic here

The telltale problem seems to be:

Failed to register mdio bus.

Looking in the emaclite driver, you can see that this error can be caused by two different issues.A good first step is to figure out which of these is the culprit. To do this, you can modify drivers/net/ethernet/xilinx/xilinx_emaclite.c in the kernel source. Specifically, try changing line 817 from:

dev_err(dev, "Failed to register mdio bus.\n");

to:

dev_err(dev, "PHY node or PHY node parent not found.\n");

After you rebuild the kernel, try booting again and post the new ethernet related boot messages

a.gamez · May 18, 2016

9 hours ago, sbobrowicz said:

We also document the PHY address in the reference manual and schematic here

True! I've found it now there, thanks

9 hours ago, sbobrowicz said:
dev_err(dev, "PHY node or PHY node parent not found.\n");
After you rebuild the kernel, try booting again and post the new ethernet related boot messages

That's been a great idea! I just did that and that's been in fact the message that appears now, so the problem lies there, on finding PHY node.

So, reading xilinx_emaclite.c code I found that I was missing phy-handle on device tree. So, my .dts file now looks like this:

                axi_ethernetlite_0: ethernet@40e00000 {
                        compatible = "xlnx,xps-ethernetlite-1.00.a";
                        device_type = "network";
                        interrupt-parent = <&microblaze_0_axi_intc>;
                        interrupts = <1 0>;
                        reg = <0x40e00000 0x10000>;
                        xlnx,duplex = <0x1>;
                        xlnx,include-global-buffers = <0x1>;
                        xlnx,include-internal-loopback = <0x0>;
                        xlnx,include-mdio = <0x1>;
                        xlnx,rx-ping-pong = <0x1>;
                        xlnx,s-axi-id-width = <0x1>;
                        xlnx,tx-ping-pong = <0x1>;
                        xlnx,use-internal = <0x0>;
                        phy-handle = <&phy0>;
                        axi_ethernetlite_0_mdio: mdio {
                                #address-cells = <1>;
                                #size-cells = <0>;
                                phy0: phy@1 {
                                        device_type = "ethernet-phy";
                                        reg = <1>;
                                };
                        };
                };

And after this, ethernet probes succesfully!

xilinx_emaclite 40e00000.ethernet: Device Tree Probing
libphy: Xilinx Emaclite MDIO: probed
xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00
xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF0140000, irq=2

Sadly, there's still something wrong. Once I configure eth0 with an ip address (ifconfig eth0 192.168.1.222), the following keeps happening:

xilinx_emaclite 40e00000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
xilinx_emaclite 40e00000.ethernet eth0: Link is Down
xilinx_emaclite 40e00000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
xilinx_emaclite 40e00000.ethernet eth0: Link is Down
xilinx_emaclite 40e00000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx
xilinx_emaclite 40e00000.ethernet eth0: Link is Down

And it doesn't stop... So we've advanced a little, but I'm now stuck again :/ What do you reckon should be the next step?

sbobrowicz · May 19, 2016

It could be the your Vivado IPI project... Compare your project against this tutorial: https://reference.digilentinc.com/arty/gsmbs

Pay attention to the interrupts and clocking. Note you have to provide a 25 MHz clock to the PHY. I would recommend testing your design by running the echo server on it in Xilinx SDK (the tutorial walks you through this setup). To do that, you will need to make sure you project has a axi_timer core with the interrupt connected (i think this is already required for Linux anyways though).

If that doesn't do it, try poking around the emaclite driver some more and see if maybe you need to add something else to your device tree. You should also double check that the interrupt is properly being referenced in the device tree, note that it depends on which pin the ethernetlite address is connected to on the concant block in front of the axi_intc.

a.gamez · May 19, 2016

12 hours ago, sbobrowicz said:

It could be the your Vivado IPI project... Compare your project against this tutorial: https://reference.digilentinc.com/arty/gsmbs

I've followed the tutorial and I can ping the ARTY, it even gets its IP via DHCP, so the hardware works fine

12 hours ago, sbobrowicz said:

Pay attention to the interrupts and clocking. Note you have to provide a 25 MHz clock to the PHY. I would recommend testing your design by running the echo server on it in Xilinx SDK (the tutorial walks you through this setup). To do that, you will need to make sure you project has a axi_timer core with the interrupt connected (i think this is already required for Linux anyways though).

I've tried running iwlp example as above on my design and it doesn't work, so I guess we can assume that there is, in fact, something wrong with my IP design. However, I can't find what it is.

Just to enumerate things, in case you notice something that is missing:

I have an axi_timer with interrupt connected to concat/In0 and uartlite with interrupt connected to concat/In3. Both of them are a requisite of Linux. I also have an SPI core connected to the flash with its interrupt routed to concat/In2. By the way, I've been able to define device tree for the flash and it's working under Linux
I have one 25 MHz clock routed to an external port named eth_ref_clk which is defined in an .xdc file to be routed to pin G18, as per GSMBS example.
EthernetLite interrupt is also routed to concat/In1

12 hours ago, sbobrowicz said:

If that doesn't do it, try poking around the emaclite driver some more and see if maybe you need to add something else to your device tree. You should also double check that the interrupt is properly being referenced in the device tree, note that it depends on which pin the ethernetlite address is connected to on the concant block in front of the axi_intc.

There's nothing else I've found on emaclite code that uses any other value from the device tree. I've also compared the device tree with one that I know works on Avnet's LX9 board.

In the end everything points to the IP design, but I can't find what's wrong...

sbobrowicz · May 19, 2016

Agreed, that likely narrows it down to your hardware project. I'll take a peak at it, do the following:

export your block diagram as a tcl script and post it here.

also attach any XDC files you are using.

one other question: are you using our arty board files? (Linked on the resource center I pointed you to earlier)

a.gamez · May 20, 2016

9 hours ago, sbobrowicz said:

Agreed, that likely narrows it down to your hardware project. I'll take a peak at it, do the following:

export your block diagram as a tcl script and post it here.

also attach any XDC files you are using.

one other question: are you using our arty board files? (Linked on the resource center I pointed you to earlier)

Yes, I'm using arty board files. As you'll see, the design is very simple in fact. I made it starting off the same GSMB tutorial but modified the microblaze core so it could run linux and I added some of the board peripherics, such as SPI, GPIO, etc.

Thanks a lot!

mb_linux_bd.tcl

eth.xdc

a.gamez · May 24, 2016

Hi!

I think I may have solved this! It seems that etherlite won't work under Linux if Enable Internal Loopback is unchecked. At least that's what's happening to me now

Now I have a different problem, which is that before lots of changes, LEDs worked for me using gpio-led module, but now they don't. I guess I have screwed something up, but in a way it's funny that I got ethernet to work but broke something as simple as the LEDs...

Best regards!

sbobrowicz · June 18, 2016

Sorry I fell off this thread, I have some issues with my notifications it appears...

I hope the LED issue got sorted out, let me know if not.

Is any of this work posted anywhere? Seems other people might be able to build on the work you've done getting Linux running :).

a.gamez · June 24, 2016

Hi!

Yes, I managed to solve the LEDs issue too. I had to use upstream linux kernel instead of that of Xilinx'... I definitely didn't expect that, but there's something wrong in there.

I'd like to post a short guide explaning what I did, but I haven't had the time yet, sorry.

sbobrowicz · July 8, 2016

Glad to hear it. If you find some time to put together a guide let us know, we can probably do some things to send some traffic your way...

fpgadeveloper · November 15, 2017

For anyone else who is interested, I've got Arty's Ethernet port working in PetaLinux and I've documented the process here:

http://www.fpgadeveloper.com/2017/11/petalinux-for-artix-7-arty-base-project.html

I've also provided a link to the boot files at the end of the article so that you can try it out yourself.

Jeff

loberman · April 15, 2018

Been meaning to document the manual Linux on Arty without petalinux fully so finally here it is.

I attached a PDF file as its easier to do it that way.

Any questions ask away.

Firstly thanks to Jeff of http://www.fpgadeveloper.com as I used his base design as the start, see above.

Ping me oberman.l@gmail.com for files, too large to attach here

Linux_on_artA7_manual_build.pdf

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