FPGA IIC HYGRO tester: IPI-BD and Verilog

[Tim S.]

Hi to the community.

I have posted on GitHub a FPGA design that polls the Pmod HYGRO via IIC and displays the sensor readings on the Pmod CLS.

https://timothystotts.github.io/2020/09/12/hygro-sensor-readings-tester-on-arty-a7.html

Regards,

Tim S.

[Tim S.]

The source code and document for this project were updated from using Xilinx Vivado/SDK 2019.1 to Xilinx Vivado/Vitis 2020.2 .

[Tim S.]

Hi to the community,

I have refreshed this design. Now with support for:

• Digilent Inc. Arty S7-25 FPGA development board containing a small Xilinx Spartan-7 FPGA
• Digilent Inc. Arty A7-100 FPGA development board containing a large Xilinx Artix-7 FPGA
• Digilent Inc. Zybo Z7-20 APSoC development board containing a moderate Xilinx Zynq-7000 SoC

There are four designs total. 3 IPI-BD designs plus a C program, one for each of the mentioned development boards. And 1 straight Verilog-HDL design that targets either of the Arty A7 and Arty S7 boards.

The examples are kept at beginner level and are based on textbook and datasheet study, as well as HDL and FPGA work experience.

The Pmod HYGRO is polled and then its readings displayed in human-readable text on the 16x2 LCD.

Read more at:

https://timothystotts.github.io/2023/04/30/refresh-of-the-fpga-iic-hygro-tester.html

Cheers.

Tim S.