Using JTAG to communicate with RISC-V Rocket in FPGA

[edwinleung]

Hi,

I am planning to load a RISC-V Rocket SoC into a Genesys2 Kintex-7 FPGA, the RISC-V Rocket SoC has a JTAG interface which allows the "outside world" to access logic in the SoC, such as reading some internal registers. I am thinking I'll route the RISC-V JTAG interface to the JTAG port of Kintex-7, which is then connected to J17 USB of the Genesys2 board,

On the other hand, I want to run chipscope to view internal signals of the RISC-V SoC for debugging purposes.  This would require connection between host computer and the FPGA, the connection used is typically through the JTAG port.

My question is do you think I can use Kintex-7 JTAG port for both functions mentioned above?

Thanks,

Edwin

 

[zygot]

13 hours ago, edwinleung said:

My question is do you think I can use Kintex-7 JTAG port for both functions mentioned above?

I have no experience with RISC-V implementation on arbitrary Xilinx FPGA platforms. My gut feeling is that you can do anything you want via JTAG. The real question here is how prepared are you to dig into your RISC-V code and make it all work. I doubt that this will be seamless but I could be wrong.

Chipscope is an ISE tool. Vivado Hardware Manager can connect to the Vivado ILA and VIO IP. Sometimes, these debugging tools are a quick and easy to use approach to debugging. Often user created debug tools work out better. It depends on what you need to capture.

I'd expect that by now there is a robust RISC-V community somewhere with better answers than I've just provided. The Genesis2 would seem to be a nice platform for this kind of project.

[xc6lx45]

I think you'll save yourself much hassle if you don't share the same physical JTAG interface. Simply take a couple of GPIOs, connect them to an FT2232H minimodule or any other hardware interface, and run a fully independent physical interface.

Otherwise, you're facing the problem that different software packages need access to the PC side of the JTAG box at the same time, and this usually does not work for the very simple reason that only one connection can be open at the same time on the PC side.

I have successfully integrated my own logic to JTAG as it's ~5x faster than UART (see BSCANE2 component and USER1..USER4 registers) but that works best when I run my own bitstream uploader out of the same software package so no other JTAG tools are needed at the same time. Having the RISC inside a USERx instruction would also require changes to e.g. the debugger code because it is not a simple hardware JTAG chain (if someone has done this already, please check their documentation).