Inout module IP block

[youngpark]

Hello,

I have a trouble with Verilog module in IP block design.  xdcrid_ is my main module which has a state machine and iobuf module is for a inout port(red wire).

To notice the current_state (state machine), I attached the leds for each state's output. In one state, xdcrEN(Green wire) get outs from the xdcrid module and this is for 'oe(enable)' signal for following module(iobuf). The state machine works well(I checked the leds for each state as desired) but outp(pupple wire) doesn't get out so that xdcr_ID doesn't work as input signals for main module.

I have no idea of what is the problem of this design. 

(currently, MDAT, Latch, Vclk is not used in this design)
 

 

 

==================<xdcrid.v module>===============================

module xdcrid(MDAT,latch,vclk,fclk, btn0, btn1, xdcr_ID, XDCRID,led0, led1, val, led2, xdcrEN);
input [7:0]MDAT;
input latch;
input vclk;
input fclk;
input btn0;
input btn1;
input [7:0] xdcr_ID;
output [7:0] XDCRID;
output [7:0] val;
output [2:0] led0;
output led1;
output led2;
output xdcrEN;

parameter idle = 3'b000, read = 3'b001, atdi = 3'b010,  passiveID = 8'b10001011;
reg [2:0]led0 ;
reg xdcrEN ;
reg led1, led2;
reg [2:0] current_state, next_state;
reg [7:0] XDCRID;
reg [7:0] val;
reg [25:0] count;

initial current_state = idle;

always@(posedge fclk) begin
    count<=count+1;
    current_state <= next_state;
    val[7:0] <= xdcr_ID[7:0];
//    if(xdcrEN ==0)
//        XDCRID[7:0] <= xdcr_ID[7:0];
end

always@(posedge fclk) begin
    case(current_state)
        idle: 
            if(btn0) begin
                next_state <= read;
                end
            else if(btn1) 
                next_state <= atdi;
            else
                next_state <= idle;
        read :
            if(btn0)            
                next_state <= idle;
            else if(btn1)
                next_state <= atdi;
            else 
                next_state <= read;
        atdi :
            if(btn0)
                next_state <= idle;
            else 
                next_state <= atdi;          
    endcase
end        

//----------------- output logic-------------------------// 
always@(posedge fclk) begin 
    case(current_state)
        idle: begin
            led0 <= 3'b000;
            led1 <= 0;
            led2 <= 1;          // 10
            xdcrEN <= 0;
            XDCRID <= 8'b00000000;     //output disable
            end
            
        read : begin
            //led0 <= 3'b101;         // 110 : blue  // 101 : red  // 011 : green
            led1 <= 1;
            led2 <= 0;          //01
            xdcrEN <= 0;
            //XDCRID[7:0] <= xdcr_ID[7:0];
            if(val != passiveID) begin       
                led0 <= 3'b011;     // green
                end
            else
                led0 <= 3'b111; //red
            end
             
        atdi : begin            // 11
            led1 <= 1;
            led2 <= 1;
            xdcrEN <= 1;
            XDCRID[7:0] <= 8'b11110000;
            if(count > 10000000)                
                led0 <= 3'b110;     //blue
            else
                led0 <= 3'b111;    // turn off
            end
            endcase
end

endmodule
 

 

 

==================<iobuf.v module>================================

module iobuf(clk,inp,outp,bidir,oe);
input clk;
input [7:0]inp;
output [7:0]outp;
inout [7:0]bidir;
input oe;

reg [7:0] a; // input
reg [7:0] b; // inout

assign bidir = oe? a : 8'bz;
assign outp = b;

always@(posedge clk)
    begin
        b <= bidir;
        a <= inp;
    end

endmodule

==================================================================================

 

I appreciate your advice.

 

-Young Park-

[JColvin]

Hi @youngpark,

I asked another engineer for their opinion on this and they recommended checking everything is being instantiated correctly; when they did a separate test they had an inout that was being instantiated as an obuf. You might try instantiating a port as a GPIO and then making it external which should create an _io port that acts as an inout.

This was the code they were testing on one of the boards they had:

Spoiler

    
/*
    When SW1 is active, JA1 acts as input and is forwarded to LD1
    When SW1 is inactive, JA1 acts as output, and BTN1 is forwarded to LD1 through JB1
   
    Test conditions:
    SW1 active, plug a jumper from JA1 into VDD and then GND
    SW1 inactive, plug a jumper from JB1 into JA1, press BTN1 to watch the LED toggle
*/
module inout_test (
    input wire sw1,
    input wire btn1,
    input wire jb1,
   
    output wire led,
   
    inout wire ja1 // tristate based on switch position
);
    wire ja1_i = ja1;
    wire ja1_o = btn1;
    wire ja1_t = sw1;
   
    assign ja1 = (ja1_t) ? 'bz : ja1_o;
    assign led = (ja1_t) ? ja1 : jb1;
endmodule

 

Thanks,
JColvin