sync logging of bus data

[Andy Rabagliati]

Folks,

 I have a new AD2, and I would like to log a data bus sequence for analysis.

First prize: 16 bit data logging, clocked in with Trig1, Triggered by Trig2.

My problem: If I use Sync mode, the data bus is just marked "X". If I use the free-running timebase, I see hex values, but I want the values on the rising clock edge.

Second problem: Can I use Trig1 as a clock, or must I burn a digital channel for the clock ?

Third: Can I start the capture on the falling edge of Reset, for repeatability ?

Must I burn another digital channel for reset as well ? I did try using Reset (burning a channel) as the Sync Channel enable, which would work in a pinch.

This functionality would be an obvious requirement on a logic analyser, and I am frustrated that I cannot find a way to do it.

 

[Andy Rabagliati]

I have found the Events view, and can write a CSV from there - is that the recommended way? I would still like 16 bits if possible.

[JColvin]

Hi @Andy Rabagliati,

I have moved your question to a more appropriate section of the forum where the engineer most familiar with the Analog Discovery 2 and the WaveForms software will be able to see and respond to your question.

Thanks,
JColvin

[attila]

Hi @Andy Rabagliati

In Sync mode trigger is not available and it uses DIO lines for clock and enable, so you won't be able to capture 16 bits of data.

In case you are using Sync mode the Data (view) will be the bus data.
If you are using other modes and Bus interpreter the Even view will list the decoded bus data.

[Andy Rabagliati]

Fortunately I am in control of the bus speed, and my solution has been to use the record mode, oversampling the DUT clock, and all 16 bits are the bus.

Slowing it down is necessary so I can manually trigger it.

I can also multiplex two values, address and data, on the same bus, so I get two channels!

Thanks for your reply, and I think my "First Prize" above might be a suggestion for the Spartan guy's next update?

The Waveforms software does a great job of dispensing with the clock, and I am very pleased with it so far.

[attila]

Hi @Andy Rabagliati

I just notice as workaround you could use the Scope in mixed mode (Add Channel/ Digital/ like Bus) and select Sampling Clock External trigger.

The Delay option is optimized to compensate the ADC/Scope latency relative to Digital/Trigger signals.
Set this to -140ns to have no Trigger to Digital sampling delay.

Later I will add such option directly in the Logic Analyzer.

Here I have connected DIO-0 to Trigger 1 but you can use other dedicated clock signal too.

[Andy Rabagliati]

Thank you - this seems to be very close to what I want.

Except ... I want the bus traffic listed in a window like the digital view, so I can follow it.

I am tracking a program being executed, and wish to follow the thread easily.

It seems like all the pieces are there, just not in all the expected places - these facilities definitely belong in the digital window.

Many thanks for all your assistance.