I am using a digilent genesys board (the board with the virtex 5 fpga). I want to save data that I read from fpga in the strataflash and then I want to read that data again form the strataflash. I have been struggling for a long time in order to read/write (even with a simple example as the one below) to the flash memory but i was not successful. It has been mentioned that a reference design on the Digilent website provides an example of driving the Flash memory in the reference manual of digilent genesys but i couldn't find it. I would appreciate any help.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAM_interface is
Port ( clock : in STD_LOGIC;
st_led: out std_logic_vector(7 downto 0);
clk_o: out std_logic;
addr_o : out STD_LOGIC_VECTOR (24 downto 0);
data_io : inout STD_LOGIC_VECTOR (15 downto 0);
--data_i : in STD_LOGIC_VECTOR (15 downto 0);
adv_o, ce_o, oe_o, we_o, reset_o : out STD_LOGIC);
end RAM_interface;
architecture Behavioral of RAM_interface is
begin
clk_o <= '0';
fsm: process(clock)
type states is (write_data_phase_1, write_data_phase_2, write_data_phase_3, read_data_phase_1, read_data_phase_2);
variable st : states:= write_data_phase_1;
variable cnt_v: integer:=0;
begin
if clock = '1' and clock'event then
case st is
when write_data_phase_1 =>
if cnt_v > 20 then st := write_data_phase_2; cnt_v := 0; else cnt_v := cnt_v + 1;
end if;
addr_o(24 downto 2) <= (others => '0');
addr_o(1 downto 0) <= "01";
--data_io(15 downto 0) <= x"1111";
--(adv_o, ce_o, oe_o, we_o,reset_o) <= "01110";
adv_o <= '0';
ce_o <= '1';
oe_o <= '1';
we_o <= '1';
reset_o <= '1';
NET "st_led[0]" LOC = "AG8" ; #Bank 22
NET "st_led[1]" LOC = "AH8" ; #Bank 22
NET "st_led[2]" LOC = "AH9" ; #Bank 22
NET "st_led[3]" LOC = "AG10" ; #Bank 22
NET "st_led[4]" LOC = "AH10" ; #Bank 22
NET "st_led[5]" LOC = "AG11" ; #Bank 22
NET "st_led[6]" LOC = "AF11" ; #Bank 22
NET "st_led[7]" LOC = "AE11" ; #Bank 22
NET "clock" LOC = "AG18" ; #Bank 22
NET "ce_o" LOC = "AE14" ; #Bank 22
NET "oe_o" LOC = "AF14" ; #Bank 22
NET "we_o" LOC = "AF20" ; #Bank 22
NET "clk_o" LOC = "AG21" ; #Bank 22
NET "reset_o" LOC = "AG17" ; #Bank 22
#NET "wait_o" LOC = "AH18" ; #Bank 22
NET "adv_o" LOC = "AF21" ; #Bank 22
NET "addr_o[0]" LOC = "K12" ; #Bank 22
NET "addr_o[1]" LOC = "K13" ; #Bank 22
NET "addr_o[2]" LOC = "H23" ; #Bank 22
NET "addr_o[3]" LOC = "G23" ; #Bank 22
NET "addr_o[4]" LOC = "H12" ; #Bank 22
NET "addr_o[5]" LOC = "J12" ; #Bank 22
NET "addr_o[6]" LOC = "K22" ; #Bank 22
NET "addr_o[7]" LOC = "K23" ; #Bank 22
NET "addr_o[8]" LOC = "K14" ; #Bank 22
NET "addr_o[9]" LOC = "L14" ; #Bank 22
NET "addr_o[10]" LOC = "H22" ; #Bank 22
NET "addr_o[11]" LOC = "G22" ; #Bank 22
NET "addr_o[12]" LOC = "J15" ; #Bank 22
NET "addr_o[13]" LOC = "K16" ; #Bank 22
NET "addr_o[14]" LOC = "K21" ; #Bank 22
NET "addr_o[15]" LOC = "J22" ; #Bank 22
NET "addr_o[16]" LOC = "L16" ; #Bank 22
NET "addr_o[17]" LOC = "L15" ; #Bank 22
NET "addr_o[18]" LOC = "L20" ; #Bank 22
NET "addr_o[19]" LOC = "L21" ; #Bank 22
NET "addr_o[20]" LOC = "AE23" ; #Bank 22
NET "addr_o[21]" LOC = "AE22" ; #Bank 22
NET "addr_o[22]" LOC = "AG12" ; #Bank 22
NET "addr_o[23]" LOC = "AF13" ; #Bank 22
NET "addr_o[24]" LOC = "AG23" ; #Bank 22
NET "data_io[0]" LOC = "AD19" ; #Bank 22
NET "data_io[1]" LOC = "AE19" ; #Bank 22
NET "data_io[2]" LOC = "AE17" ; #Bank 22
NET "data_io[3]" LOC = "AF16" ; #Bank 22
NET "data_io[4]" LOC = "AD20" ; #Bank 22
NET "data_io[5]" LOC = "AE21" ; #Bank 22
NET "data_io[6]" LOC = "AE16" ; #Bank 22
NET "data_io[7]" LOC = "AF15" ; #Bank 22
NET "data_io[8]" LOC = "AH13" ; #Bank 22
NET "data_io[9]" LOC = "AH14" ; #Bank 22
NET "data_io[10]" LOC = "AH19" ; #Bank 22
NET "data_io[11]" LOC = "AH20" ; #Bank 22
NET "data_io[12]" LOC = "AG13" ; #Bank 22
NET "data_io[13]" LOC = "AH12" ; #Bank 22
NET "data_io[14]" LOC = "AH22" ; #Bank 22
NET "data_io[15]" LOC = "AG22" ; #Bank 22
Question
Anis
Hello everyone,
I am using a digilent genesys board (the board with the virtex 5 fpga). I want to save data that I read from fpga in the strataflash and then I want to read that data again form the strataflash. I have been struggling for a long time in order to read/write (even with a simple example as the one below) to the flash memory but i was not successful. It has been mentioned that a reference design on the Digilent website provides an example of driving the Flash memory in the reference manual of digilent genesys but i couldn't find it. I would appreciate any help.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity RAM_interface is
Port ( clock : in STD_LOGIC;
st_led: out std_logic_vector(7 downto 0);
clk_o: out std_logic;
addr_o : out STD_LOGIC_VECTOR (24 downto 0);
data_io : inout STD_LOGIC_VECTOR (15 downto 0);
--data_i : in STD_LOGIC_VECTOR (15 downto 0);
adv_o, ce_o, oe_o, we_o, reset_o : out STD_LOGIC);
end RAM_interface;
architecture Behavioral of RAM_interface is
begin
clk_o <= '0';
fsm: process(clock)
type states is (write_data_phase_1, write_data_phase_2, write_data_phase_3, read_data_phase_1, read_data_phase_2);
variable st : states:= write_data_phase_1;
variable cnt_v: integer:=0;
begin
if clock = '1' and clock'event then
case st is
when write_data_phase_1 =>
if cnt_v > 20 then st := write_data_phase_2; cnt_v := 0; else cnt_v := cnt_v + 1;
end if;
addr_o(24 downto 2) <= (others => '0');
addr_o(1 downto 0) <= "01";
--data_io(15 downto 0) <= x"1111";
--(adv_o, ce_o, oe_o, we_o,reset_o) <= "01110";
adv_o <= '0';
ce_o <= '1';
oe_o <= '1';
we_o <= '1';
reset_o <= '1';
when write_data_phase_2 =>
if cnt_v > 10 then st := write_data_phase_3; cnt_v := 0; else cnt_v := cnt_v + 1;
end if;
--addr_o(24 downto 2) <= (others => '0');
--addr_o(1 downto 0) <= "01";
data_io(15 downto 0) <= x"1111";
--(adv_o, ce_o, oe_o, we_o,reset_o) <= "01110";
adv_o <= '0';
ce_o <= '0';
oe_o <= '1';
we_o <= '0';
reset_o <= '1';
when write_data_phase_3 =>
if cnt_v > 0 then st := read_data_phase_1; cnt_v := 0; else cnt_v := cnt_v + 1;
end if;
--addr_o(24 downto 2) <= (others => '0');
--addr_o(1 downto 0) <= "01";
--data_io(15 downto 0) <= x"1111";
--(adv_o, ce_o, oe_o, we_o,reset_o) <= "01110";
adv_o <= '0';
ce_o <= '1';
oe_o <= '1';
we_o <= '1';
reset_o <= '1';
when read_data_phase_1 =>
if cnt_v > 1 then st := read_data_phase_2; cnt_v := 0; else cnt_v := cnt_v + 1;
end if;
addr_o(24 downto 2) <= (others => '1');
addr_o(1 downto 0) <= "00";
--(adv_o, ce_o, oe_o, we_o,reset_o) <= "00011";
adv_o <= '0';
ce_o <= '0';
oe_o <= '0';
we_o <= '1';
reset_o <= '1';
--wait_o <= '1';
when read_data_phase_2 =>
if cnt_v > 7 then st := read_data_phase_2; cnt_v := 0; else cnt_v := cnt_v + 1;
end if;
addr_o(24 downto 2) <= (others => '0');
addr_o(1 downto 0) <= "01";
--(adv_o, ce_o, oe_o, we_o,reset_o) <= "00011";
adv_o <= '0';
ce_o <= '1';
oe_o <= '1';
we_o <= '1';
reset_o <= '1';
--wait_o <= 'Z';
when others =>
addr_o(24 downto 2) <= (others => '0');
addr_o(1 downto 0) <= "00";
--(adv_o, ce_o, oe_o, we_o,reset_o) <= "00011";
adv_o <= '1';
ce_o <= '1';
oe_o <= '1';
we_o <= '1';
reset_o <= '1';
--wait_o <= 'Z';
end case;
end if;
end process;
st_led <= data_io(7 downto 0);
end Behavioral;
and this is the constraint file:
NET "st_led[0]" LOC = "AG8" ; #Bank 22
NET "st_led[1]" LOC = "AH8" ; #Bank 22
NET "st_led[2]" LOC = "AH9" ; #Bank 22
NET "st_led[3]" LOC = "AG10" ; #Bank 22
NET "st_led[4]" LOC = "AH10" ; #Bank 22
NET "st_led[5]" LOC = "AG11" ; #Bank 22
NET "st_led[6]" LOC = "AF11" ; #Bank 22
NET "st_led[7]" LOC = "AE11" ; #Bank 22
NET "clock" LOC = "AG18" ; #Bank 22
NET "ce_o" LOC = "AE14" ; #Bank 22
NET "oe_o" LOC = "AF14" ; #Bank 22
NET "we_o" LOC = "AF20" ; #Bank 22
NET "clk_o" LOC = "AG21" ; #Bank 22
NET "reset_o" LOC = "AG17" ; #Bank 22
#NET "wait_o" LOC = "AH18" ; #Bank 22
NET "adv_o" LOC = "AF21" ; #Bank 22
NET "addr_o[0]" LOC = "K12" ; #Bank 22
NET "addr_o[1]" LOC = "K13" ; #Bank 22
NET "addr_o[2]" LOC = "H23" ; #Bank 22
NET "addr_o[3]" LOC = "G23" ; #Bank 22
NET "addr_o[4]" LOC = "H12" ; #Bank 22
NET "addr_o[5]" LOC = "J12" ; #Bank 22
NET "addr_o[6]" LOC = "K22" ; #Bank 22
NET "addr_o[7]" LOC = "K23" ; #Bank 22
NET "addr_o[8]" LOC = "K14" ; #Bank 22
NET "addr_o[9]" LOC = "L14" ; #Bank 22
NET "addr_o[10]" LOC = "H22" ; #Bank 22
NET "addr_o[11]" LOC = "G22" ; #Bank 22
NET "addr_o[12]" LOC = "J15" ; #Bank 22
NET "addr_o[13]" LOC = "K16" ; #Bank 22
NET "addr_o[14]" LOC = "K21" ; #Bank 22
NET "addr_o[15]" LOC = "J22" ; #Bank 22
NET "addr_o[16]" LOC = "L16" ; #Bank 22
NET "addr_o[17]" LOC = "L15" ; #Bank 22
NET "addr_o[18]" LOC = "L20" ; #Bank 22
NET "addr_o[19]" LOC = "L21" ; #Bank 22
NET "addr_o[20]" LOC = "AE23" ; #Bank 22
NET "addr_o[21]" LOC = "AE22" ; #Bank 22
NET "addr_o[22]" LOC = "AG12" ; #Bank 22
NET "addr_o[23]" LOC = "AF13" ; #Bank 22
NET "addr_o[24]" LOC = "AG23" ; #Bank 22
NET "data_io[0]" LOC = "AD19" ; #Bank 22
NET "data_io[1]" LOC = "AE19" ; #Bank 22
NET "data_io[2]" LOC = "AE17" ; #Bank 22
NET "data_io[3]" LOC = "AF16" ; #Bank 22
NET "data_io[4]" LOC = "AD20" ; #Bank 22
NET "data_io[5]" LOC = "AE21" ; #Bank 22
NET "data_io[6]" LOC = "AE16" ; #Bank 22
NET "data_io[7]" LOC = "AF15" ; #Bank 22
NET "data_io[8]" LOC = "AH13" ; #Bank 22
NET "data_io[9]" LOC = "AH14" ; #Bank 22
NET "data_io[10]" LOC = "AH19" ; #Bank 22
NET "data_io[11]" LOC = "AH20" ; #Bank 22
NET "data_io[12]" LOC = "AG13" ; #Bank 22
NET "data_io[13]" LOC = "AH12" ; #Bank 22
NET "data_io[14]" LOC = "AH22" ; #Bank 22
NET "data_io[15]" LOC = "AG22" ; #Bank 22
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