1116345 Posted December 27, 2014 Share Posted December 27, 2014 Hello, can someone help me with this error?? Thanks in advance code: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity PWM is port( clr : in STD_LOGIC; clk : in STD_LOGIC; duty : out STD_LOGIC; period : out STD_LOGIC; pwm : out STD_LOGIC ); end PWM; architecture PWM of PWM is component clkdiv port( mclk : in STD_LOGIC; clr : in STD_LOGIC; clk1 : out STD_LOGIC; clk95 : out STD_LOGIC ); end component; signal count : STD_LOGIC; begin U1 : clkdiv port map( mclk => clk, clr => clr, clk1 => period, clk95 => duty); end; begin <-------------------------------------------------------ERROR IS HERE clk4 : process(clk, clr) begin if clr = '1' then count <= (others => '0'); elsif clk'event and clk = '1' then if count = period -1 then count <= (others => '0'); else count <= count + 1; end if ; end if ; end process clk4; pwmout: process(count,duty) begin if count < duty then pwm <= '1'; else pwm <= '0'; end if ; end process pwmout; end PWM; code for clkdiv: library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity clkdiv is port( mclk : in STD_LOGIC; clr : in STD_LOGIC; clk1 : out STD_LOGIC ; clk95 : out STD_LOGIC ); end clkdiv; architecture clkdiv of clkdiv is signal q: STD_LOGIC_VECTOR (23 downto 0); begin process (mclk,clr) begin if clr= '1' then q <= X"000000" ; elsif mclk'event and mclk = '1' then q <= q + 1; end if ; end process; clk1 <= q(5); clk95 <= q(19); end clkdiv; ERROR: # Error: COMP96_0016: PWM.vhd : (35, 4): Design unit declaration expected. Link to comment Share on other sites More sharing options...
hamster Posted January 14, 2015 Share Posted January 14, 2015 Hi! You might want to read up on what a 'generate' loop actually does. L1: for i in 1 to 8 generate P1 <= s; end generate L1; L2: for i in 9 to 16 generate P2 <= s; end generate L2; ... Gens expanded into P1 <= s; -- Code when i = 1 P1 <= s; -- Code when i = 2 P1 <= s; -- Code when i = 3 P1 <= s; -- Code when i = 4 P1 <= s; -- Code when i = 5 P1 <= s; -- Code when i = 6 P1 <= s; -- Code when i = 7 P1 <= s; -- Code when i = 8 P2 <= s; -- Code when i = 9 P2 <= s; -- Code when i = 10 P2 <= s; -- Code when i = 11 P2 <= s; -- Code when i = 12 P2 <= s; -- Code when i = 13 P2 <= s; -- Code when i = 14 P2 <= s; -- Code when i = 15 P2 <= s; -- Code when i = 16 So the loops in your code are just saying the same thing 8 times.. To make them do something useful need to use the loop variable (in this case 'i') somewhere in the block of code being repeated. For example, here is how you could code the 8 flip flops for your shift register in far few lines, with less chance for error: U0: Dff port map (clk => clk, Din => Din, Q => s(0) ); gen_ffs: for i in 1 to 7 generate Ui: Dff port map (clk => clk, Din => s(i-1), Q => s(i)); end generate L2; Link to comment Share on other sites More sharing options...
hamster Posted December 27, 2014 Share Posted December 27, 2014 Get rid of both these lines: end; begin <-------------------------------------------------------ERROR IS HERE Link to comment Share on other sites More sharing options...
1116345 Posted December 28, 2014 Author Share Posted December 28, 2014 Hello I did try this and the number of errors just increased.... ERRORS: # Error: COMP96_0077: PWM.vhd : (38, 13): Undefined type of expression. Expected type 'STD_ULOGIC' # Error: COMP96_0071: PWM.vhd : (40, 23): Operator "-" is not defined for such operands. # Error: COMP96_0077: PWM.vhd : (40, 7): Undefined type of expression. Expected type 'BOOLEAN'. # Error: COMP96_0077: PWM.vhd : (41, 14): Undefined type of expression. Expected type 'STD_ULOGIC'. # Error: COMP96_0071: PWM.vhd : (43, 22): Operator "+" is not defined for such operands. # Error: COMP96_0077: PWM.vhd : (43, 14): Undefined type of expression. Expected type 'STD_ULOGIC'. # Error: COMP96_0264: PWM.vhd : (49, 19): Signal "duty" in the sensitivity list must denote a signal that can be read. Link to comment Share on other sites More sharing options...
hamster Posted December 28, 2014 Share Posted December 28, 2014 Hello I did try this and the number of errors just increased.... ERRORS: # Error: COMP96_0077: PWM.vhd : (38, 13): Undefined type of expression. Expected type 'STD_ULOGIC' # Error: COMP96_0071: PWM.vhd : (40, 23): Operator "-" is not defined for such operands. # Error: COMP96_0077: PWM.vhd : (40, 7): Undefined type of expression. Expected type 'BOOLEAN'. # Error: COMP96_0077: PWM.vhd : (41, 14): Undefined type of expression. Expected type 'STD_ULOGIC'. # Error: COMP96_0071: PWM.vhd : (43, 22): Operator "+" is not defined for such operands. # Error: COMP96_0077: PWM.vhd : (43, 14): Undefined type of expression. Expected type 'STD_ULOGIC'. # Error: COMP96_0264: PWM.vhd : (49, 19): Signal "duty" in the sensitivity list must denote a signal that can be read. Yep, now that your code is structurally correct (with all the right 'begin's and 'end's), the compiler is now telling you about things that you are asking it to implement that do not make sense to do. Here's a few * Your "count" signal is a single bit, so your can't do addition on it, nor can you assign '0' to all it's elements (e.g. your code "count <= (others => '0');") - for that you will need 'count' to be a STD_LOGIC_VECTOR of a suitable length. * You are doing a comparison between 'count' and 'duty' ("if count < duty then"). Both are signal bits. * Both 'Duty' and 'Period' are declared as "OUT" at line 11. You won't be able to use them as variables withing the processes, only assign values to them, I also notice that the errors are generated by the ALDEC VHDL toolset, As Digilent are pretty much a Xilinx shop for their FPGA products I think you might have found yourself in the wrong neighborhood - it is quite unlikely that you are using their products with those tools! Link to comment Share on other sites More sharing options...
1116345 Posted December 29, 2014 Author Share Posted December 29, 2014 Hi, I tried another code but I am getting errors again . Can you please help me out?? CODE: library IEEE; use IEEE.STD_LOGIC_1164.all; entity pwm is port( clr : in STD_LOGIC; clk : in STD_LOGIC; pwm : out STD_LOGIC ); end pwm; architecture pwm of pwm is signal count: STD_LOGIC_VECTOR (7 downto 0); signal duty: STD_LOGIC_VECTOR (7 downto 0); signal period: STD_LOGIC_VECTOR (7 downto 0); begin P1: process (clk,clr) begin count <= X"00"; duty <= X"64"; -------------------------------------------------------------------------ERROR period <= X"F3"; -------------------------------------------------------------------------ERROR if clr = '1' then count <= (others =>'0') ; elsif clk'event and clk = '1' then if count = period - 1 then count <= count + 1; end if; end if; end process P1; pwmout: process (count) begin if count < duty then pwm <= '1'; else pwm <='0'; end if; end process pwmout; end pwm; ERRORS: # Error: COMP96_0015: pwm.vhd : (24, 12): ';' expected. # Error: COMP96_0015: pwm.vhd : (25, 14): ';' expected. Link to comment Share on other sites More sharing options...
JColvin Posted December 29, 2014 Share Posted December 29, 2014 Hi 1116345, The issue that you are running into here is that your program doesn't know how to interpret (what I presume to be) your hexadecimal code for the value of your STD_LOGIC_VECTOR. What the compiler is expecting in that line is a binary sequence telling it which value each of the 8 bits are, so for your X"64" you would need to write "01000000". This will assign those values to the eight bits in the order that you declared them, so duty(6) would be the bit with a value of 1. There is likely a way to "typecast" your code so that the compiler understands what you are telling it, but after a doing a bit of looking, there doesn't seem to be a way to "directly" do this, although there are several available workarounds that I found via googling "STD_LOGIC_VECTOR with hexadecimal". Let me know if you have any more questions. Thanks, JColvin Link to comment Share on other sites More sharing options...
1116345 Posted January 14, 2015 Author Share Posted January 14, 2015 Hello Mr JColvin, I rewrote the codes for serial to parallel conversion but problem is that I am able to convert only 1 8-bit parallel..the other 6 outputs are just similar.. My serial input in simulation is 20 bit so basically I should have at least 2 8-bit parallel output but thats not the case :/ please can you help ??? library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; use IEEE.STD_LOGIC_arith.all; entity SIPO is generic (N: integer := 7); port( clk : in STD_LOGIC; Din : in STD_LOGIC; Q :out STD_LOGIC_VECTOR(7 downto 0); P1 : out STD_LOGIC_VECTOR(7 downto 0); P2 : out STD_LOGIC_VECTOR(7 downto 0); P3 : out STD_LOGIC_VECTOR(7 downto 0); P4 : out STD_LOGIC_VECTOR(7 downto 0); P5 : out STD_LOGIC_VECTOR(7 downto 0); P6 : out STD_LOGIC_VECTOR(7 downto 0); P7 : out STD_LOGIC_VECTOR(7 downto 0) ); end SIPO; architecture SIPO of SIPO is component Dff is port ( clk : in STD_LOGIC; Din : in STD_LOGIC; Q : out STD_LOGIC ); end component; signal s: std_logic_vector (7 downto 0); signal i: integer := 1; constant num_cycles: integer := 56; begin M1 : for i in 1 to num_cycles generate u0: Dff port map ( clk => clk, Din => Din, Q => s(0) ); u1: Dff port map ( clk => clk, Din => s(0), Q => s(1) ); u2: Dff port map ( clk => clk, Din => s(1), Q => s(2) ); u3: Dff port map ( clk => clk, Din => s(2), Q => s(3) ); u4: Dff port map ( clk => clk, Din => s(3), Q => s(4) ); u5: Dff port map ( clk => clk, Din => s(4), Q => s(5) ); u6: Dff port map ( clk => clk, Din => s(5), Q => s(6) ); u7: Dff port map ( clk => clk, Din => s(6), Q => s(7) ); end generate M1; L1: for i in 1 to 8 generate P1 <= s; end generate L1; L2: for i in 9 to 16 generate P2 <= s; end generate L2; L3: for i in 17 to 24 generate P3 <= s; end generate L3; L4: for i in 25 to 32 generate P4 <= s; end generate L4; L5: for i in 33 to 40 generate P5 <= s; end generate L5; L6: for i in 41 to 48 generate P6 <= s; end generate L6; L7: for i in 49 to 56 generate P7 <= s; end generate L7; end SIPO; Link to comment Share on other sites More sharing options...
1116345 Posted January 14, 2015 Author Share Posted January 14, 2015 Sir, Doing this surely reduces the code lines but how to get the other parallel outputs???? Link to comment Share on other sites More sharing options...
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1116345
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can someone help me with this error?? Thanks in advance
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