Channeling I2C, SPI, and UART signals to I/O pins on Cora Z7

[emma9513]

I am trying to use a DAQ to analyze I2C, SPI, and UART signals and then classify them, so they have to be the actual output signals from the Cora Z7 board. However, I am limited due to the project itself to use only the General Purpose I/O pins (IO0-IOA(IO42)). Is it possible to funnel the SPI, I2C, and UARt signals through these pins, or can you only use the specified pins, such as SDA/SCL, MISO/MOSI, or the USB UART bridge to do this?

[Ana-Maria Balas]

Hello @emma9513,

The Shield Connector have SPI and I2C dedicated pins. However there is no issue if you want to use the General Purpose I/O pins.

You can use the EMIO for SPI, I2C and UART1 from Zynq PS then constrain them to the desired IO pins.

Also you can use AXI Quad SPI IP, AXI IIC IP and AXI Uartlite then constrain them to the desired IO pins.

I recommend using the first way if you want one interface per communication protocol and also you won't fill the PL with unnecessary logic if you have a big project.

Let me know if you have problems.

Cheers,

Ana-Maria

[emma9513]

@Ana-Maria Balas,

 

Thanks for your reply! If I am using the GPIO pins for I2C, will I need to account for the pull-up resistors that the dedicated I2C pins have?

[Ana-Maria Balas]

If you  don't use a shield which comes equipped with pull-up resistors pre-installed, then yes, you will have to add the pull-up resistors externally.

But since the I2C pins on the Shield Connector are so close to IO, why bother ?

[emma9513]

@Ana-Maria Balas I am adding a custom physical device/shield that when added will only allow access to the GPIO pins and the I2C pins will be blocked with no physical or electrical access. What is the value of the internal pull-up resistors? I can't see to find it in the documentation?

[Ana-Maria Balas]

You can see the schematic of the board on the resource center.

I2C pins are right beside IO42, so i think it is convenient for your project...

EDIT: @emma9513 I just remembered that you can add pull-up resistors internally from FPGA and constrain those pins in xdc.

 

 

 

[Ana-Maria Balas]

Something like this :

set_property -dict { PACKAGE_PIN U14   IOSTANDARD LVCMOS33   PULLUP TRUE} [get_ports { scl }]; #IO_L11P_T1_SRCC_34 Sch=ck_io[0]
set_property -dict { PACKAGE_PIN V13   IOSTANDARD LVCMOS33   PULLUP TRUE} [get_ports { sda }]; #IO_L3N_T0_DQS_34 Sch=ck_io[1]