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Found 6 results

  1. I am using a Cora Z7-10 board and have a sandbox project (Verilog) that can boot using an external SD card without issue. When I launch Vitis and import any UART example into my project, I can run that via JTAG and see that all of the examples work fine. I then create a boot.bin, that includes the fsbl, the bitstream, and the example.elf files - the FPGA does not boot properly. I can see that the Verilog circuit is working, but the UART example isn't. I am powering the board via USB, and I have confirmed that the baud rate and COM port is correct when running the examples using JTAG. I've attached the boot image and the bif file. Any help would be much appreciated. Boot_and_bif.zip
  2. Hello, We are trying to add the Cora Z7 as a custom board into Matlab to allow model based development. We have been following this guide: define-and-register-custom-board-and-reference-design-for-zynq-workflow, but are getting stuck at linking to the Linux bit (the last step); (step 4 of section 'Integrate the IP core with the Xilinx Vivado environment' referenced here Getting Started with Targeting Xilinx Zynq Platform). We have Petalinux installed on an SD card, and can ssh into this etc., but its missing the necessary matlab customisation. We need to either use build root, or customise the Petalinux build. From Mathworks: So my questions are: Does anyone have a built image for the Cora Z7 using either of these methods? / a Linux image that we can use for this board with Matlab?. Can we use buildroot with the Cora Z7, such as by using the Zybo as an example and adapting this to suit the Cora? HAs anyone tried this? Does anyone have experience of the drivers necessary for Matlab, and how to add these to and rebuild the Petalinux kernel source? Cheers, Sean.
  3. How do I compute the energy consumed in Digilent Cora Z7 board on executing a code in the PS part, that also accesses the PL? I found the steps to measure power in ZC702 board in this link: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842356/Zynq-7000+AP+SoC+Low+Power+Techniques+part+3+-+Measuring+ZC702+Power+with+a+Standalone+Application+Tech+Tip Is there any standard library/code that can be used for Cora Z7 board?
  4. Hello, I'm trying to output a differential signal using the PMOD pins on my board. My attempts so far have been unsuccessful. I just have a simple test set up which creates a differential clock signal using the Verilog shown below. module top ( input clk, output clk_test, output clk_test_n ); generate OBUFDS #(.IOSTANDARD("LVDS_25")) obufds_test(.I(clk), .O(clk_test), .OB(clk_test_n)); endgenerate And I map these signal to two PMOD pins. set_property -dict { PACKAGE_PIN W14 IOSTANDARD LVCMOS33 } [get_ports { clk_test }]; #IO_L8P_T1_34 Sch=jb_p[1] set_property -dict { PACKAGE_PIN Y14 IOSTANDARD LVCMOS33 } [get_ports { clk_test_n }]; #IO_L8N_T1_34 Sch=jb_n[1] The documentation talks a lot about inputting differential signals but nothing about driving them. Is this possible?
  5. I am new to this so I am just guessing how to out stuff together. I want to use the PmodI2S2 for Stereo Audio Input and Output. I am using a Cora z7 with a ZYNQ. I want to try and make two things: A. Connect the PmodI2S2 via Axi and then write a software application in Vitis to send and receive audio data. B. Connect the Pmod12S2 to logic and modify audio data. Possibly make an oscillator. The "Pmod I2S2 FPGA Volume Control Demo" in the resources centre says it uses an AXI streaming interface. So for part A. I made a new IP with an AXI streaming interface (just one way for line out) and a Pmod output that wraps some of the example code (removing the loop back bit). Then I connected it to DMA. and the DMA to the zynq. Not sure if this makes sense to do.. design_2.pdf But then I am not sure how I get the address in vitis. do I just use the dma address ? I can't work out how it is all translated/mapped. Or.... should I be using a FIFO/ buffer in hardware and writing larger amount of data at a time ?? Is AXI streaming correct should I use something else ? When I create new IP I have the choice: Lite/Full/Stream but when I edit the IP in the packager and add interfaces the AXI interfaces have the following: What is what in here ?? For Part B The example loopback code uses the AXI streaming interface, but what should I use in logic or what would be a normal design for moving audio samples around in fpga ?? Any help
  6. Aswa

    Clock output in Cora Z7

    Hello, I am using a Cora Z7-10 board for outputting a 5 MHz clock to IO0 pin of the Arduino/Chipkit Shield connector. But I am not getting a perfect square. In my code, I am only outing the 5 MHz clock which is a PL fabric clock, no other logic. It would be great if anyone can tell me what should be the problem? I am attaching the capture I obtained in scope for your reference. Thanks a lot in advance.
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