I do use the DigitalDiscovery logic analyzer to capture data from an ADC. I trigger the capturing via a rising edge at DIN15.
The timing diagram looks always the same like this:
Blue is the trigger for the logic analyzer / Yellow indicates the ADC clock / Red is the sampled data
The ADC transmits the data serially (via 2 wires) to the DigiDisco-Logic inputs. After the transmission I decode the data, starting from sample one and plot the ADC sampled data.
What I expect is a plot like this - starting with 01010101011111....
What I get is different for each capture as shown below.:
- It seems like the trigger or start of capturing has a certain variation or delay.
- It is capturing data BEFORE! the trigger signal occurs
- I am sampling with 400MHz the DigiDisco DIN channels, this means there are more than 100 samples taken BEFORE! the trigger is coming.
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HoWei
I do use the DigitalDiscovery logic analyzer to capture data from an ADC. I trigger the capturing via a rising edge at DIN15.
The timing diagram looks always the same like this:
Blue is the trigger for the logic analyzer / Yellow indicates the ADC clock / Red is the sampled data
The ADC transmits the data serially (via 2 wires) to the DigiDisco-Logic inputs. After the transmission I decode the data, starting from sample one and plot the ADC sampled data.
What I expect is a plot like this - starting with 01010101011111....
What I get is different for each capture as shown below.:
- It seems like the trigger or start of capturing has a certain variation or delay.
- It is capturing data BEFORE! the trigger signal occurs
- I am sampling with 400MHz the DigiDisco DIN channels, this means there are more than 100 samples taken BEFORE! the trigger is coming.
Is this delay/variation expected ?
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