How to use DDR3L memory on Cora Z7

[RFtmi]

On Cora Z7 board, there is an IC that is named "DDR3L memory". How can I use this memory block to write and read data? How can I instantiate it in Vivado? What is the size of the memory? What is the read/write speed? 
Is there any other way to have a relatively large memory block (100 MBytes for example ) with with at least 5 MHz write speed? 

My question is sort of general now. So any other board that could do the job, or if you know how to get a 10 MBytes instead of 100, or any other relevant info. will help.

Also, if there is an example code or project that you could refer me to would be great.

 

There is also a "Block memory generator" IP in Vivado. Is this related to the external memory on the board or it's for making a memory out of internal memory cells of the FPGA?

[jpeyron]

Hi @RFtmi,

The DDR3 is connected to the ZYNQ Processor as described in the reference manual.  In section 4  DDR3L Memory of the reference manual it describes the DDR3's bus width as well as the frequency. The Digilent board files correctly configure the DDR3  in the Zynq processor and is usable in the PS.  

The Block memory uses internal resources. Here is the Block Memory Generator v8.3 LogiCORE IP Product Guide that has more detailed information.  Here are the GitHub Digilent Cora projects. 

best regards,

Jon

[RFtmi]

Thank you for the response. It answered most of my questions. So I should be able to write codes in SDK to access the DDR3 memory through the processor. What is the library that I should use and is there an example of the basic functions for read and write into the memory?

[jpeyron]

Hi @RFtmi,

Here is a youtube video that discusses using the memory in SDK.

best regards,

Jon

[RFtmi]

Thanks for the video.

Short version:

When I access the DDR through the processor it is not sync with the hardware and is limited to the program speed of the processor. In other word, if I have a bunch of sampled data that are generated by the FPGA (programmable logic) and I want to store all of them in DDR, I need to write a sample at each clock cycle, but processor can not do that. Is there a way to access the DDR directly through the hardware?

 

Long version:

As a test design, I created a 16-bit counter and added that as a module to my IP design and connected it to the processor through a GPIO. Thus, the output of the counter is accessible by the processor. I used

Xil_Out16(XPAR_PS7_DDR_0_S_AXI_BASEADDR+n*2,sigOut);

and

sigOut = Xil_In16(XPAR_PS7_DDR_0_S_AXI_BASEADDR+n*2)

(n is the index of a for loop that goes for 100 iterations) to first write 100 consecutive readout of the counter to the DDR and then read it and looked at it on the terminal. It seems that every 44 counts are picked up by the processor probably because processor runs the code slower or it takes 44 cycles to go over the for loop and thus I miss the intermediate counter values.

To capture all the samples generated by the hardware I need to access the DDR directly through the FPGA hardware. How can I do this?

To first

[jpeyron]

Hi @RFtmi,

The only resource I can find would be using a microblaze processor to communicate to the DDR3 in the PL as describe here. I have not effectively worked with microblaze on a zynq processor. Here is a resource that might be helpful. Here is a tutorial that might be helpful as well.

best regards,

Jon