Nexys4 DDR- USB-UART Bridge (J6)

[shahad]

Hi
I designed a project in the Xilinx blocks then convert it to Vivado 2017.4 as IP, The problem is, i cant make synchronization between TX and RX by using the two FPGA Nexys4 DDR, Can I use the USB-UART Bridge (J6) to solve this problem? Note that neither microblaze nor the axi is used

[jpeyron]

Hi @shahad,

In Digilent Artix-7 fpga development boards  like the Nexys 4 DDR you are able to use the USB UART bridge with VHDL/Verilog. Here is the resource center for the Nexys 4 DDR.  Here is a Verilog project that uses the USB UART bridge with the Nexys 4 DDR.

best regards,

Jon

[shahad]

@jpeyron

Thank you very much for your cooperation